View SAA7115_926980.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary nda required preliminary file under cs-pd hamburg, pc-p contents subject to change without notice. 23 oct 2001 cs-pd hamburg philips semiconductors SAA7115 cvip2 pal/ntsc/secam video decoder with adaptive pal/ntsc comb filter, high performance scaler, i2c sliced data readback and sq pixel output datasheet
preliminary nda required con?dential - nda required page 2 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 contents 1 document info. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 video acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 combfilter video decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.3 video scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 vbi data slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.5 clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.6 general features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.7 summary saa7114 versus SAA7115. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 quick reference data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 7 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.1 pinning list and pinning diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 7.2 pin configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 SAA7115 pin strapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1 decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1.1 analog input processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.1.1.1 clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1.1.2 gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.1.2 chrominance and luminance processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 8.1.2.1 chrominance path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 8.1.2.2 luminance path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.1.2.3 brightness contrast saturation (bcs) control and decoder output levels . . . . . . . . . . . 38 8.1.3 synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.1.4 clock generation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.1.5 power-on reset and chip enable (ce) input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.2 output formatter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 8.3 scaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 8.3.1 acquisition control and task handling (subaddresses 80h, 90h, 91h, 94h to 9fh and c4h to cfh) 50 8.3.1.1 input field processing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8.3.1.2 task handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.3.1.3 output field processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 8.3.2 horizontal scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.3.2.1 horizontal prescaler (subaddresses a0h to a7h and d0h to d7h) . . . . . . . . . . . . . . . 55 8.3.2.2 horizontal fine scaling (variable phase delay filter; subaddresses a8h to afh and d8h to dfh)60 8.3.3 vertical scaling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.3.3.1 line fifo buffer (subaddresses 91h, b4h and c1h, e4h) . . . . . . . . . . . . . . . . . . . . . 60 8.3.3.2 vertical scaler (subaddresses b0h to bfh and e0h to efh) . . . . . . . . . . . . . . . . . . . . 61 8.3.3.3 use of the vertical phase offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.4 vbi-data decoder and capture (subaddresses 40h to 7fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.4.1 vbi data slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 8.4.2 i2c readback of sliced vbi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
preliminary nda required con?dential - nda required page 3 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.4.3 sliced vbi data output at the i-port. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.4.3.1 euro wst, us wst and nabts data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.4.3.2 wss 625 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.4.3.3 wss 525 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.4.3.4 vps data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.4.3.5 closed caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.4.3.6 moji data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.4.3.7 vitc data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.4.3.8 open data types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 8.5 image port output interface (subaddresses 84h to 87h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 8.5.1 scaler output formatter (subaddresses 93h and c3h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.5.2 video fifo (subaddress 86h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.5.3 text fifo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.5.4 video / text arbitration and data packing (subaddress 86h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.5.4.1 vbi insertion in sav/eav mode (bit sldom[3] = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.5.4.2 data packing (bit impak (86h) and programming of the pulse generator via addr. f5h to fbh)73 8.5.5 data stream coding and reference signal generation (subaddresses 84h, 85h and 93h) . . . . . . 73 8.6 scaler backend clock generation (subaddresses 30h to 3fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 8.6.1 square pixel clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.6.1.1 the second pll (pll2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 8.7 audio clock generation (subaddresses 30h to 3fh). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.7.1 audio clock generation without analog pll (cgc2) enhancement . . . . . . . . . . . . . . . . . . . . . . . . 82 8.7.1.1 master audio clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.7.1.2 signals asclk and alrclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 8.7.2 audio clock generation with analog pll (cgc2) support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 8.7.3 other control signals for audio clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 9 input/output interfaces and ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.1 analog terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.2 audio clock signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 9.3 clock and real-time synchronization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 9.4 video expansion port (x-port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 9.4.1 x-port configured as output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 9.4.2 x-port configured as input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.5 image port (i-port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 9.6 host port for 16-bit extension of video data i/o (h-port) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 9.7 basic input and output timing diagrams i-port and x-port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.7.1 i-port output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.7.2 x-port input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 10 boundary scan test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.1 initialization of boundary scan circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 10.2 device identification codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 11 limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 12 thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 13 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 14 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 15 device programming overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 15.1 i2c-bus description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 15.2 register overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 16 detailed description of the control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
preliminary nda required con?dential - nda required page 4 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.1 chip version / ident register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 16.1.1 chip version. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 16.1.2 chip id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 16.2 programming register decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 16.2.1 subaddress 01 analog input control 0, increment delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 16.2.2 subaddress 02 analog input control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 16.2.3 subaddress 03 analog input control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 16.2.4 subaddress 04 analog input control 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 16.2.5 subaddress 05 analog input control 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 16.2.6 subaddress 06 horizontal sync start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 16.2.7 subaddress 07 horizontal sync stop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 16.2.8 subaddress 08 sync control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 16.2.9 subaddress 09 luminance control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 16.2.10 subaddress 0a decoder brightness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 16.2.11 subaddress 0b decoder contrast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 16.2.12 subaddress 0c decoder saturation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 16.2.13 subaddress 0d chrominance hue. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 16.2.14 subaddress 0e chrominance control 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 16.2.15 subaddress 0f chrominance gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 16.2.16 subaddress 10 chrominance/luminance control 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 16.2.17 subaddress 11 mode / delay control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 16.2.18 subaddress 12 rts0/1 output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 16.2.19 subaddress 13 and 1b rt / x-port output control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 16.2.20 subaddress 14 analog / adc / auto/ compatibility control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 16.2.21 subaddress 15, 17vgate start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 16.2.22 subaddress 16, 17 vgate stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 16.2.23 subaddress 17 misc./vgate-msbs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 16.2.24 subaddress 18 raw data gain control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 16.2.25 subaddress 19 raw data offset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 16.2.26 subaddress 1a color killer level control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 16.2.27 subaddress 1b misc. chroma control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 16.2.28 subaddress 1c enhanced combfilter control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 16.2.29 subaddress 1d enhanced combfilter control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 16.2.30 subaddresses 1e, 1f status bytes video decoder (read-only register) . . . . . . . . . . . . . . . . . . . 157 16.3 programming register audio clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 16.3.1 subaddresses 30 to 32 amclk cycles per field . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 16.3.2 subaddresses 34 to 36 amclk nominal increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 16.3.3 subaddress 38 ratio amxclk to asclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 16.3.4 subaddress 39 ratio asclk to alrclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 16.3.5 subaddress 3a audio clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 16.4 programming register vbi data slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 16.4.1 subaddress 40 basic slicer settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 16.4.2 subaddress 41 to 57 line control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 16.4.3 subaddress 58 programmable framing code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 16.4.4 subaddress 59 horizontal offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 16.4.5 subaddress 5a vertical offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 16.4.6 subaddress 5b field offset, msbs h/v-offsets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 16.4.7 subaddress 5d: sldom codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 16.4.8 subaddress 5e sdid codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 16.4.9 subaddress 5e (read-only register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 16.4.10 subaddress 66 to 7f i2c readback of decoded vbi data (read-only register). . . . . . . . . . . . . . 167 16.4.10.1 subaddress 66 to 6a i2c readback of closed caption data (cc525 and cc625) (read-only register)167 16.4.10.2 subaddress 6b to 71 i2c readback of closed caption data (wss525 and wss625)
preliminary nda required con?dential - nda required page 5 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 (read-only register)168 16.4.10.3 subaddress 72 to 76 i2c readback of gemstar1x data (read-only register) . . . . . . . 169 16.4.10.4 subaddress 77 to 7f i2c readback of gemstar2x data (read-only register) . . . . . . . 170 16.5 programming register - interfaces and scaler part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 16.5.1 subaddress 80: global settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 16.5.2 subaddress 83 to 87: global interface configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 16.5.3 subaddress 88: sleep and power save control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 16.5.4 subaddress 8f (read-only register): status information scaler part . . . . . . . . . . . . . . . . . . . . . . . 181 16.5.5 subaddress 90: event handler control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 16.5.6 subaddress 91 to 93: scaler input and i-port output configuration. . . . . . . . . . . . . . . . . . . . . . . . 182 16.5.7 subaddress 94 to 9b: scaler input acquisition window definition . . . . . . . . . . . . . . . . . . . . . . . 185 16.5.8 subaddress 9c to 9f: scaler output window definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 16.5.9 subaddress a0 to a2: prescaling and fir filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8 16.5.10 subaddress a4 to a6: brightness, contrast and saturation control . . . . . . . . . . . . . . . . . . . . . . 190 16.5.11 subaddress a8 to ae: horizontal phase scaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1 16.5.12 subaddress b0 to bf: vertical scaling control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 16.6 programming register - second pll (pll2) and pulse generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 16.6.1 subaddress f0 to f5 and ff: second pll (pll2) programming parameters . . . . . . . . . . . . . . 194 16.6.2 subaddress f6 to fb: pulse generator programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 17 programming start set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.1 decoder part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 17.2 audio clock generation part. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 17.3 data slicer and data type control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 17.4 scaler and interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 17.4.1 examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 17.5 pll2 and pulse generator control part . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 18 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214
preliminary nda required con?dential - nda required page 6 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 1 document info 1.1 revision history 2 features 2.1 video acquisition six analog inputs, internal analog source selectors, (e.g.: 6x cvbs or(2 x yc and 2 cvbs) or (1 x yc and 4xcvbs) two built in analog anti-alias filters two improved 9 bit cmos analog-to-digital converter in differential cmos style at two-fold itu-656 oversampling (27mhz) fully programmable static gain or automatic gain control (agc) for the selected cvbs or y/c channel automatic clamp control (acc) for cvbs, y and c switchable white peak control two 9-bit video cmos ad converters, digitized cvbs or y/c signals are available on the expansion port (x-port) requires only one crystal (32.11 mhz or 24.576 mhz) for all standards independent gain and offset - adjustment for raw data path 2.2 comb?lter video decoder digital pll for synchronization and clock generation from all standards and non standard video sources e.g. consumer grade vtr automatic detection of 50/60hz field frequency, and automatic recognition of all common broadcast standards enhanced horizontal and vertical sync detection luminance and chrominance signal processing for C pal bgdhin, C combination-pal n, C pal m, C ntsc m, C ntsc-japan, C ntsc 4.43 and C secam (50 hz / 60 hz) pal delay line for correcting pal phase errors version no revision date description of status by 0.5 5 oct 2001 initial version h. lambers 0.51 9 oct 2001 fixed lcbw recommended setting h. lambers 0.52 9 oct 2001 vbsl setting changed, scaler and pll2 examples , sect. 16.4 and 16.5 updated a. mittelberg 0.6 10 oct 2001 added application examples h. lambers 0.65 18 oct 2001 status at cqs h. lambers 0.66 19 oct 2001 minor updates h. lambers 0.67 23 oct 2001 fixed application example drawing h. lambers
preliminary nda required con?dential - nda required page 7 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 improved 2/4-line comb filter for two dimensional chrominance/luminance-separation operating with adaptive combfilter parameters. C increased luminance and chrominance bandwidth for all pal and ntsc-standards C reduced cross colour and cross luminance artefacts independent brightness contrast saturation (bcs) - adjustment for decoder-part user programmable sharpness control detection of copy protected input signals: C according to macrovision standard C indicating the level of protection automatic tv/vcr detection 10 bit wide video output at combfilter video decoder x-port video output either as: C noise shaped 8 bit itu-656 video or C full 10 bit itu-656 interface (dc-performance 9 bit) 2.3 video scaler horizontal and vertical down-scaling and up-scaling to randomly sized windows horizontal and vertical scaling range: variable zoom to 1/64 (icon) (note: h and v zoom are restricted by the transfer data rates) vertical scaling with linear phase interpolation and accumulating filter for anti-aliasing (6 bit phase accuracy) conversion to square pixel format generation of a video output stream with improved synchronisation grid at the i-port two independent programming sets for scaler part, to define two "ranges" per field or sequences over frames fieldwise switching between decoder-part and expansion port (x-port) input brightness, contrast and saturation controls for scaled outputs 2.4 vbi data slicer versatile vbi-data decoder, slicer, clock regeneration and byte synchronization, e.g. for: C wst525 / wst625 (ccst) C vps C us / european close caption (cc), C wss525 (cgms), wss625, C us nabts C vitc 525 / vitc 625 C gemstar 1x C gemstar 2x C moji i 2 c readback of the following decoded data types: C us close caption (cc) C european close caption (cc)
preliminary nda required con?dential - nda required page 8 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 C wss525 (cgms) C wss625 (cgms) C gemstar 1x C gemstar 2x 2.5 clock generation on-chip line locked clock generation according itu601 generation of a frame locked audio master clock to support a constant number of audio clocks per video field. second onboard analog pll to be used for: C on-chip line locked square pixel clock generation for pal and ntsc square pixel video output or C optionally generation of a low jitter frame locked audio clock from the audio master clock through reuse of the analog square pixel pll. supported audio clock frequencies are 256*fs, 384*fs and 512*fs (fs = 32 khz, 44.1 khz or 48 khz). 2.6 general features cmos 3.3 v device with 5 v tolerant digital inputs and i/o ports programming via serial i 2 c-bus, full read-back ability by an external controller, bit rate up to 400 kbit/s software controlled power saving stand-by modes boundary scan test circuit complies to the ieee std. 1149.b1 -1994
preliminary nda required con?dential - nda required page 9 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 2.7 summary saa7114 versus SAA7115 table 1 saa7114 versus SAA7115 issue saa7114 SAA7115 pin compatibility reference pinning pin-compatible to saa7114 analog frontend 2 x 9 bit a/d- converters 2 x low noise 9 bit a/d- converters 13.5 mhz ccir sampling 27 mhz ccir 2x-oversampling standard white-peak control watching raw data standard white-peak control watching raw data plus baseband luminance data comb?lter decoder 4 lines adaptive comb ?lter improved 4 lines adaptive comb ?lter (reduced artifacts) manual tv/vcr switching automatic tv/vcr detection semi-automatic color standard detection fully-automatic color standard detection regular secam 50 hz regular secam 50 hz and secam 60 hz (vietnam) color over?ow detection automatic color reducer (avoids color limitation with low burst) safe lock for vcr feature modes extended safe lock for vcr feature modes fast frame lock (ca. 2 ?elds) ultra-fast frame lock (almost 1 ?eld) macrovision detection pseudo sync.macrovision detection only comprehensive macrovision detection: - pseudo sync. detection and/or - split burst detection (type 2 / type 3) scaled video output generation of embedded itu-656 auxiliary codes at the i-port video output generation of embedded itu-656 auxiliary codes at the i-port video output with improved synchronization raster for vcr signals clock generation scaling to square pixel data representation scaling to square pixel data representation with extra integrated clock-pll (pll2, cgc2) to generate physical square pixel clock signal of 29.5 mhz (pal) or 24.5454 mhz (ntsc). field- locked audio clock (constant number of clock cycles per ?eld) frame- locked audio clock (constant number of clock cycles per frame), optionally through analog pll (cgc2) vbi data slicing and output versatile vbi- data slicer versatile vbi- data slicer, incl. cgms (line 20 ntsc) and gemstar 2x (epg) output of sliced data embedded into i-port output stream output of sliced data embedded into i-port output stream and optionally per i2c register readback for cc, cgms, gemstar1x and gemstar2x,
preliminary nda required con?dential - nda required page 10 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 3 general description the SAA7115 is a video capture device for various applications ranging from small screen products like e.g. digital settop boxes, personal video recording applications to big screen devices like e.g. lcd projectors due to its improved combfilter performance and 10 bit video output capabilities. the SAA7115 is a combination of a two channel analog preprocessing circuit including source-selection, anti-aliasing filter and a/d-converter, an automatic clamp and gain control, two clock generation circuits (cgc1, cgc2), a digital multi standard decoder containing two-dimensional chrominance/luminance separation by an improved adaptive comb filter and a high performance scaler, including variable horizontal and vertical up and down scaling and a brightness- contrast- saturation- control circuit. the decoder is based on the principle of line-locked clock decoding and is able to decode the colour of pal, secam and ntsc signals into itu-601 compatible colour component values. the SAA7115 accepts as analog inputs cvbs or s-video (y-c) from tv or vcr sources, including weak and distorted signals. the expansion port (x-port) for digital video (bi-directional half duplex, d1 compatible) can be used either to output unscaled video using 10 bit or 8 bit dithered resolution or to connect to other external digital video sources for reuse of the SAA7115 scaler features. the enhanced image port (i-port) of the 7115 supports 8 (16) bit wide output data with auxiliary reference data for interfacing to e.g. vga controllers, settop box applications etc. it is also possible to output video in square pixel formats accompanied by a square pixel clock of the appropriate frequency. in parallel SAA7115 incorporates also provisions for capturing the serially coded data in the vertical blanking interval (vbi-data) of several standards. three basic options are available to transfer the vbi data to other devices: capturing raw video samples, after interpolation to the required output data rate, using the scaler and transferring the data to a device connected to the i-port, slicing the vbi data using the build in vbi data slicer (data recovery unit) and transferring the data to a device connected to the i-port slicing the vbi data using the build in vbi data slicer and reading out the sliced data via the i 2 c bus (for several slow vbi data type standards only) SAA7115 incorporates also a frame locked audio clock generation. this function ensures that there is always the same number of audio samples associated with a frame, or a set of fields. this prevents the loss of sychronisation between video and audio, during capture or playback. furthermore the second analog onboard pll optionally can be used to enhance this audio clock to a low jitter frame locked audio clock. the SAA7115 is controlled via i 2 c-bus (full write / read capability for all programming registers, bit rate up to 400 kbits/s)
preliminary nda required con?dential - nda required page 11 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 4 quick reference data 5 ordering information symbol parameter min typ max unit v ddx digital supply voltage 3.0 3.3 3.6 v v ddcx digital supply voltage range core 3.0 3.3 3.6 v v dda analog supply voltage range 3.1 3.3 3.5 v t amb ambient temperature range 0 - 70 c p a+d analog and digital power consumption (1) 1. power consumption is measured in cvbs-input mode (only one adc active) and 8 bit image port output mode, expansion port is tristated - t.b.d. - w extended type number package pins pin position material code SAA7115 100 lqfp100 plastic sot407-cd5
preliminary nda required con?dential - nda required page 12 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 6 block diagram analog dual adc line fifo buffer fir - pre?lter horizontal scaling rt out iic video fifo 32 mux 8(16) to programming register array a / b mux reg. general purpose vbi data slicer event controller video / text arbiter x port i/o formatting frame locked pll expansion port pin mapping image port pin mapping digital decoder boundary test scan xtri ipd[7:0] igpv xrdy llc llc2 rtco rts0 rts1 hpd[7:0] test1 test2 test5 test4 test3 ai11 ai12 ai21 ai22 ai23 ai24 trstn tck tms tdi tdo axmclk alrclk asclk *) amclk *) igph idq test0 aout xtalo xtali xtout ce reson clock generation and power on control the pins rtco and alrclk de?nition of the crystal osc. note: scl sda prescaler fine (phase) text fifo of the iic interface and the are used for con?guration frequency at reset block diagram SAA7115 with adaptive comb ?lter i/o control (pin strapping) and scaler bcs vertical scaling xclk xdq xpd[7:0] xrh *) xrv *) igp1 igp0 itri itrdy iclk vddi vdde vdda vssi vsse vssa agnd 30 27 4 7 6 20 18 16 14 12 10 22 19 ai1d ai2d 13 28 29 36 34 35 94 95 81,82, 92 91 96 80 84-87, 89,90 64-67, 69-72 32 31 79 78 77 74 73 44 53 46 48 52 47 42 54-57, 59-62 45 49 97 98 99 3 2 37 40 39 41 33,43, 58,68, 83,93 1,25, 51,75 11,17, 23 38,63, 88 26,50, 76,100 9,15, 24 vxdd vxss 8 5 fig.1 SAA7115 block diagram pll2 audio clock cgc2 audio clock generation puls generator
preliminary nda required con?dential - nda required page 13 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 7 pinning 7.1 pinning list and pinning diagram table 2 pinning list SAA7115 symbol pin i/o/p description v dde 1 p digital supply voltage 3.3 v (external pad supply) tdo 2 o test data output for boundary scan test (2) tdi 3 i test data input for boundary scan test (with internal pull-up) (2) xtout 4 o crystal oscillator output signal, auxiliary signal v xss 5p ground pin for crystal oscillator xtalo 6 o 24.576 (32.11) mhz crystal oscillator output; not connected if xtali is driven by an external single-ended oscillator. xtali 7 i input terminal for 24.576 (32.11) mhz crystal oscillator or connection of exter- nal oscillator with ttl compatible square wave clock signal. v xdd 8p supply voltage pin of crystal oscillator v ssa2 9p ground for analog inputs ai2x ai24 10 i analog input 24 v dda2 11 p analog supply voltage for analog inputs ai2x (3.3v) ai23 12 i analog input 23 ai2d 13 i differential input for adc channel 2 (pins ai24, ai23, ai22, ai21) ai22 14 i analog input 22 v ssa1 15 p ground for analog inputs ai1x ai21 16 i analog input 21 v dda1 17 p analog supply voltage for analog inputs ai1x (3.3v) ai12 18 i analog input 12 ai1d 19 i differential input for adc channel 1 (pins ai12, ai11) ai11 20 i analog input 11 agnd 21 p analog ground connection aout 22 o analog test output (do not connect) v dda0 23 p analog positive supply voltage for both internal cgc (clock generation cir- cuit) (3.3v) v ssa0 24 p analog ground for internal cgc
preliminary nda required con?dential - nda required page 14 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 v dde 25 p digital supply voltage 3.3 v (external pad supply) v sse 26 p digital ground (external pad supply) ce 27 i chip enable or reset input (with internal pull up) llc 28 o line-locked system clock output (27 mhz nominal), for backward compatibility, do not use for new applications llc2 29 o line locked clock/2 output (13.5 mhz nominal) for backward compatibility, do not use for new applications reson 30 o reset output not signal scl 31 i (/o) iic serial clock line (with inactive output path) sda 32 i/o iic serial data line v ddi 33 p digital supply voltage 3.3 v internal core supply) rts0 34 o real time status or sync information, controlled by subaddr. 11h and 12h rts1 35 o real time status or sync information, controlled by subaddr. 11h and 12h rtco 36 (i/) o real time control output: contains information about actual system clock frequency, ?eld rate, odd/even sequence, decoder status, subcarrier phase and frequency and pal sequence (according to rtc level 3.1, refer to external document rtc functional speci?cation for details), can be strapped to supply via a 3.3 kohm resistor to change the default iic-wr-addresses from 42/43 (internal pull down) to 40/41. amclk 37 o audio master clock output v ssi 38 p digital ground (internal core supply) asclk 39 o audio serial clock output alrclk 40 (i/) o audio left/right clock output, can be strapped to supply via a 3.3 kohm resistor indicate that the default 24.576 mhz crystal (internal pull down) has been replaced by a 32.11 mhz crystal. amxclk 41 i audio master external clock input (typing error corrected) itrdy 42 i target ready input, image port (with internal pull up) v ddi 43 p digital supply voltage 3.3 v (internal core supply) test0 44 o do not connect, reserved for future extensions and for testing: scan output iclk 45 i/o clock output signal for image-port, lclk of lpb image port mode, or optional asynchron. backend clock input idq 46 o output data qualifier for image port (optional: gated clock output) symbol pin i/o/p description
preliminary nda required con?dential - nda required page 15 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 itri 47 i (/o) image-port output control signal, effects all i-port pins incl. iclk, enable and active polarity is under software control (bits ipe in subaddr. 87) output path used for testing : scan output igp0 48 o general purpose output signal 0; image-port (controlled by subaddr. 84,85) igp1 49 o general purpose output signal 1; image-port (controlled by subaddr. 84,85), same functions as igp0 v sse 50 p digital ground (external pad supply) v dde 51 p digital supply voltage 3.3 v (external pad supply) igpv 52 o multi purpose vertical reference output signal; image-port (controlled by subaddr. 84,85) igph 53 o multi purpose horizontal reference output signal; image-port (controlled by subaddr. 84,85) ipd7 ipd6 ipd5 ipd4 54 55 56 57 o o o o image port data output v ddi 58 p digital supply voltage 3.3 v (internal core supply) ipd3 ipd2 ipd1 ipd0 59 60 61 62 o o o o image port data output v ssi 63 p digital ground (internal core supply) hpd7 hpd6 hpd5 hpd4 64 65 66 67 i/o i/o i/o i/o host port data i/o, carries uv chrominance information in 16 bit video i/o modes v ddi 68 p digital supply voltage 3.3 v (internal core supply) hpd3 hpd2 hpd1 hpd0 69 70 71 72 i/o i/o i/o i/o host port data i/o, carries uv chrominance information in 16 bit video i/o modes test1 73 i do not connect, reserved for future extensions and for testing: scan input symbol pin i/o/p description
preliminary nda required con?dential - nda required page 16 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 test2 74 i do not connect, reserved for future extensions and for testing: scan input v dde 75 p digital supply voltage 3.3 v (external pad supply) v sse 76 p digital ground (external pad supply) test3 77 i do not connect, reserved for future extensions and for testing: scan input test4 78 o do not connect, reserved for future extensions and for testing: scan output test5 79 i do not connect, reserved for future extensions and for testing: scan input xtri 80 i x-port output control signal, effects all x-port pins (xpd[7:0], xrh, xrv, xdq and xclk) enable and active polarity is under software control (bits xpe in subaddr. 83) xpd7 xpd6 81 82 i/o i/o expansion-port data: in eight bit video output mode: these signal represent the video bits 7 to 6. in ten bit video output mode: these signal represent the video bits 9 to 8. v ddi 83 p digital supply voltage 3.3 v (internal core supply) xpd5 xpd4 xpd3 xpd2 84 85 86 87 i/o i/o i/o i/o expansion-port data: in eight bit video output mode: these signal represent the video bits 5 to 2. in ten bit video output mode: these signal represent the video bits 7 to 4. v ssi 88 p digital ground (internal core supply) xpd1 xpd0 89 90 i/o i/o expansion-port data: in eight bit video output mode: these signal represent the video bits 1 to 0. in ten bit video output mode: these signal represent the video bits 3 to 2. xrv 91 i/o vertical reference i/o expansion-port: in ten bit video output mode: this signal represents the video bit 0. xrh 92 i/o horizontal reference i/o expansion-port: in ten bit video output mode: this signal represents the video bit 1. v ddi 93 p digital supply voltage 3.3 v (internal core supply) xclk 94 i/o clock i/o expansion port xdq 95 i/o data quali?er i/o expansion port xrdy 96 o task ?ag or read signal from scaler, controlled by xrqt (subaddr. 83h) trstn 97 i test reset not for boundary scan test (with internal pull-up); for board design without boundary scan connect trstn to ground (1) symbol pin i/o/p description
preliminary nda required con?dential - nda required page 17 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 notes 1. this pin provides easy initialization of bst circuitry. trstn can be used to force the tap (test access port) controller to the test-logic-reset state (normal operation) at once 2. according to the ieee1149.b1-1994 standard the pads tdi and tms are input pads with a internal pull-up transistor and tdo a tri-state output pad. tck, trstn are also build with internal pull_up tck 98 i test clock for boundary scan test (with internal pull-up) (2) tms 99 i test mode select for boundary scan test or scan test (with internal pull-up) (2) v sse 100 p digital ground (external pad supply) symbol pin i/o/p description
preliminary nda required con?dential - nda required page 18 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 fig.2 pinning of the SAA7115 SAA7115 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 75 74 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 hpd0 hpd1 hpd2 hpd3 hpd4 hpd5 hpd6 hpd7 ipd0 ipd1 ipd2 ipd3 ipd4 ipd5 ipd6 ipd7 v dde xtalo xtali v dda0 v ssa0 v ssa2 ai24 v dda2 ai23 ai2d ai22 v ssa1 ai21 v dda1 ai12 ai1d ai11 agnd aout v dde llc llc2 v ddi rts0 test0 iclk v sse tck test3 trstn xpd0 xpd1 xpd2 xpd3 xpd4 test5 test4 xrv preliminary 78 77 76 v ddi v sse v ddi v ssi v ddi v sse v dde v ddi v ssi v ddi v sse v xdd v xss v dde xtout tdi xrdy xdq xpd5 xpd6 xpd7 xclk igph igpv test1 itrdy idq v ssi rts1 tdo amclk ce sda itri asclk alrclk test2 tms xrh xtri reson amxclk scl igp0 igp1 rtco
preliminary nda required con?dential - nda required page 19 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 7.2 pin con?gurations table 3 pin con?gurations pin no pin name 8 bit input modes 16 bit input modes alternative input functions 8 bit output modes 16 bit output modes alternative output functions i/o con?guration prog. bits 81,82 84-87 89,90 xpd7...0 d1 data input y data input d1 decoder output [7:0] xcode[92[3]] xpe[83[1:0]] + pin xtri ofts[1b[4], 13[2:0]] d1 decoder output [9:2] 10-bit mode xcode[92[3]] xpe[83[1:0]] + pin xtri ofts[1b[4], 13[2:0]] 94 xclk clock input gated clock input decoder clock output xpe[83[1:0]} + pin xtri xpck[83[5:4]] xcks[92[0]], 95 xdq data quali?er input data quali- ?er output (href &&vref gate) xdq[92[1]] xpe[83[1:0]] + pin xtri 96 xrdy input ready output active task a/b ?ag xrqt[83[2]] xpe[83[1:0]] + pin xtri 92 xrh h-ref. input decoder h-ref output xdh[92[2]] xpe[83[1:0]] + pin xtri d1 decoder output [1] 10-bit mode xdh[92[2]] xpe[83[1:0]] + pin xtri ofts[1b[4], 13[2:0]] 80 xrv v-ref. input decoder v-ref output xdv[92[5:4]] xpe[83[1:0]] + pin xtri d1 decoder output [0] 10-bit mode xdv[92[5:4]] xpe[83[1:0]] + pin xtri ofts[1b[4], 13[2:0]] 80 xtri output enable input xpe[83[1:0]] 64-67 69-72 hpd7...0 uv data input uv scaler output icode[93[7]] iswp[85[7:6]] icks[80[3:2]] ipe[87[1:0]] + pin itri 54-57 59-62 ipd7...0 d1 scaler output y scaler- output icode[93[7]] iswp[85[7:6]] icks[80[3:2]] ipe[87[1:0]] + pin itri 45 iclk clock output clock input icks[80[1:0]] ipe[87[1:0]] + pin itri icks[80[3:2]] 46 idq data quali- ?er output gated clock out- put icks[80[3:2]] idqp[85[0]] ipe [87[1:0]] + pin itri 42 itrdy target ready input
preliminary nda required con?dential - nda required page 20 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 7.3 SAA7115 pin strapping table 4 SAA7115 pin strapping note 1. pin strapping is done by connecting the pin to supply via a 4.7 kohm resistor. during the power up reset sequence the corresponding pins are switched to input-mode to read the strapping level. for the default setting no strapping resistor is necessary (internal pull down) 53 igph h-gate out- put extended h-gate, h- pulses idh[84[1:0]] irhp[85[1]] ipe[87[1:0]] + pin itri 52 igpv v-gate output v-sync, v-pulses idv[84[3:2]] irvp[85[2]] ipe[87[1:0]] + pin itri 49 igp1 general pur- pose idg1[86[5],84[7:6]] ig1p[85[4]] ipe [87[1:0]] + pin itri 48 igp0 general pur- pose idg0[86[4],84[5:4]] ig0p[85[3]] ipe[87[1:0]] + pin itri 47 itri output ena- ble input pin no pin name function 36 rtco operates as iicsa pin, 0 = sa 42/43 hex (default), 1 = sa 40/41 hex 40 alrclk 0 = 24.576 mhz crystal (default) 1 = 32.110 mhz crystal pin no pin name 8 bit input modes 16 bit input modes alternative input functions 8 bit output modes 16 bit output modes alternative output functions i/o con?guration prog. bits
preliminary nda required con?dential - nda required page 21 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8 functional description 8.1 decoder 8.1.1 a nalog input processing the SAA7115 offers six analog signal inputs, two analog main channels with source switch, clamp circuit, analog amplifier, anti-alias filter and video 9-bit cmos adc with a decimation filter (df); see figs 4 and 7. the anti-alias filters are adapted to the line-locked clock frequency via a filter control circuit. the characteristic is shown in fig.3. during the vertical blanking period gain and clamping control are frozen. fig.3 anti-alias filter. 6 v (db) - 42 024 68101214 f (mhz) mgd138 - 6 - 12 - 18 - 24 - 30 - 36 0
preliminary nda required con?dential - nda required page 22 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5 gain (db) f (mhz) fig.4 decimation filter.
preliminary nda required con?dential - nda required page 23 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.1.1.1 clamping the clamp control circuit controls the correct clamping of the analog input signals. the coupling capacitor is also used to store and filter the clamping voltage. an internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. the clamping levels for the two adc channels are fixed for luminance (120), chrominance (256) and for component inputs as component y (32), components p b and p r (256). the clamping time is defined by the internally generated hcl pulse on the back porch of the video signal. 8.1.1.2 gain control the gain control circuit receives (via the i 2 c-bus) the static gain levels for the two analog amplifiers or controls one of these amplifiers automatically via a built-in automatic gain control (agc) as part of the analog input control (aico). the agc (automatic gain control for luminance) is used to amplify a cvbs or y signal to the required signal amplitude, matched to the adcs input voltage range. the agc active time is the sync bottom of the video signal and is defined by the internally generated hsy pulse. signal (white) peak control limits the gain at signal overshoots. the flow charts (see figs 8 and 9) show more details of the agc. the influence of supply voltage variation within the specified range is automatically eliminated by clamp and automatic gain control. handbook, halfpage hcl mhb726 hsy analog line blanking tv line 1 120 511 gain clamp fig.5 analog line with clamp (hcl) and gain range (hsy).
preliminary nda required con?dential - nda required page 24 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 fig.6 automatic gain range. analog input level controlled adc input level maximum minimum range 9 db 0 db 0 db mhb325 + 3 db - 6 db (1 v (p-p) 18/56 w )
preliminary nda required con?dential - nda required page 25 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 fig.7 analog input processing using the SAA7115 as differential front-end with 9-bit adc. ai23 ai21 fuse (1:0) fuse [1:0] aosl (2:0) holdg analog control gai1[8:0] vbsl chroma cvbs/y vertical blanking control source switch clamp circuit analog amplifier anti-alias filter bypass switch source switch clamp circuit analog amplifier anti-alias filter bypass switch adc 2 test selector clamp control gain control cross multiplexer adc 1 anti-alias control aout mode control mode [3:0] gai2[8:0] gudl[1:0] gafix wpoff hsy vblnk svref hcl buffer + dac9 dac9 hlnrs uptcv glimb glimt wipa sltca 9 9 differential frontend with 9 bit adcs ai2d 9 9 ai12 ai11 ai1d ai22 ai24 bpfout1 bpfout2 (test signals from pll1/pll2) decimation filter 1 decimation filter 2 ofts (3:0) xpd[7:0], xrh processed video
preliminary nda required con?dential - nda required page 26 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 handbook, full pagewidth analog input amplifier anti-alias filter adc luma/chroma decoder x hsy > 510 > 510 < 1 < 4 > 496 x = 0 x = 1 - 1/llc2 + 1/llc2 - 1/llc2 + / - 0 + 1/f + 1/l gain accumulator (18 bits) actual gain value 9-bit (agv) [ - 3/ + 6 db ] x stop hsy y update fgv mhb728 agv gain value 9-bit 1 0 1 0 10 1 0 1 0 1 0 10 1 0 0 1 1 0 1 0 vblk 1 0 no action 9 9 dac gain holdg fig.8 gain flow chart. x = system variable. . gudl = gain update level (adjustable). vblk = vertical blanking pulse. hsy = horizontal sync pulse. agv = actual gain value. fgv = frozen gain value. y agv fgv C gudl > =
preliminary nda required con?dential - nda required page 27 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 fig.9 clamp and gain flow chart. wipe = white peak level (510). sbot = sync bottom level (1). cll = clamp level [120 for cvbs, y(c), s; 256 for c(y), p b -p r ; 32 for rgb, y]. hsy = horizontal sync pulse. hcl = horizontal clamp pulse. 10 + clamp - clamp no clamp 10 10 01 10 mgc647 fast - gain slow + gain + gain - gain hcl hsy adc sbot wipe cll analog input gain -> <- clamp vblk no blanking active 10
preliminary nda required con?dential - nda required page 28 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.1.2 c hrominance and luminance processing 8.1.2.1 chrominance path the 9-bit cvbs or chrominance input signal is fed to the input of a quadrature demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 1 (0 and 90 phase relationship to the demodulator axis). the frequency is dependent on the chosen colour standard. the time-multiplexed output signals of the multipliers are low-pass filtered (low-pass 1). eight characteristics are programmable via lcwb3 to lcwb0 to achieve the desired bandwidth for the colour difference signals (pal, ntsc) or the 0 and 90 fm signals (secam). fig.10 chrominance and luminance processing. cvbs-in code secs huec dcvf quadrature demodulator pal-dly-line demod. phase detector amplitude accu burst gate low pass 1 loop filter subcarrier increment generation subcarrier generation 2 & divider fctc cstd[2:0] incs rtco secam- gain control uv- adjustment recombination secam- processing f h /2 switch signal downsampling adaptive comb filter ccomb ycomb ldel byps lufi[3:0] low pass 2 chbw chroma uv low pass 3 interpolation lubw uv quadrature modulator cdto subcarrier generation 1 chr.-incr. dto-reset chr.-incr. delay ldel ycomb uv subtractor delay comp. cvbs-in chr luminance- lcbw[2:0] peaking or low pass, cstd[2:0] ydel[2:0] y y/cvbs y-delay adjust. dsat[7:0] dcon[7:0] dbri[7:0] brightness contrast saturation control raw data gain & offset control rawg[7:0] rawo[7:0] acgc cgain[6:0] idel[3:0] ldel ycomb colo y-out / cvbs-out uv-out href-out set_raw set_vbi set_raw set_vbi or y-in or chr-in set_raw set_vbi set_raw set_vbi uv hodg vedg medg cmbt vedt detector colorstripe burst colstr, type3
preliminary nda required con?dential - nda required page 29 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 the chrominance low-pass 1 characteristic also influences the grade of cross-luminance reduction during horizontal colour transients (large chrominance bandwidth means strong suppression of cross-luminance). if the y-comb filter is disabled by ycomb = 0 the filter influences directly the width of the chrominance notch within the luminance path (a large chrominance bandwidth means wide chrominance notch resulting in a lower luminance bandwidth). the low-pass filtered signals are fed to the adaptive comb filter block. the chrominance components are separated from the luminance via a two line vertical stage (four lines for pal standards) and a decision logic and mixing stage between the filtered and the non-filtered output signals. the decision logic can be fine adjusted by the control signals hodg, vedg, medg, vedt and cmbt. this block is bypassed for secam signals. the comb filter logic can be enabled independently for the succeeding luminance and chrominance processing by ycomb (subaddress 09h, bit 6) and/or ccomb (subaddress 0eh, bit 0). it is always bypassed during vbi or raw data lines programmable by the lcrn registers (subaddresses 41h to 57h); see section 8.4. the separated c b -c r components are further processed by a second filter stage (low-pass 2) to modify the chrominance bandwidth without influencing the luminance path. its characteristic is controlled by chbw (subaddress 10h, bit 3). for the complete transfer characteristic of low-passes 1 and 2 see figs 11 and 12. the secam processing (bypassed for qam standards) contains the following blocks: baseband bell filters to reconstruct the amplitude and phase equalized 0 and 90 fm signals phase demodulator and differentiator (fm-demodulation) de-emphasis filter to compensate the pre-emphasized input signal, including frequency offset compensation (db or dr white carrier values are subtracted from the signal, controlled by the secam switch signal). the succeeding chrominance gain control block amplifies or attenuates the c b -c r signal according to the required itu 601/656 levels. it is controlled by the output signal from the amplitude detection circuit within the burst processing block. the burst processing block provides the feedback loop of the chrominance pll and contains the following: burst gate accumulator colour identification and colour killer comparison nominal/actual burst amplitude (pal/ntsc standards only) loop filter chrominance gain control (pal/ntsc standards only) loop filter chrominance pll (only active for pal/ntsc standards) pal/secam sequence detection, h/2-switch generation. the increment generation circuit produces the discrete time oscillator (dto) increment for both subcarrier generation blocks. it contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e.g. for non-standard signals). the pal delay line block eliminates crosstalk between the chrominance channels in accordance with the pal standard requirements. for ntsc colour standards the delay line can be used as an additional vertical filter. if desired, it can be switched off by dcvf = 1. it is always disabled during vbi or raw data lines programmable by the lcrn registers (subaddresses 41h to 57h); see section 8.4. the embedded line delay is also used for secam recombination (cross-over switches). the colorstripe burst detector detects partly or fully phase inverted burst according to the macrovision standard. the protection level is reported by the status flags colstr and type3.
preliminary nda required con?dential - nda required page 30 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 mhb533 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 v (db) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (mhz) (1) (2) (3) (4) (5) (6) (7) (8) fig.11 transfer characteristics of the chrominance low-pass at chbw = 0. (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
preliminary nda required con?dential - nda required page 31 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 mhb534 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 v (db) 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 f (mhz) (1) (2) (3) (4) (5) (6) (7) (8) fig.12 transfer characteristics of the chrominance low-pass at chbw = 1. (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
preliminary nda required con?dential - nda required page 32 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.1.2.2 luminance path the rejection of the chrominance components within the 9-bit cvbs or y input signal is achieved by subtracting the remodulated chrominance signal from the cvbs input. the comb filtered c b -c r components are interpolated (upsampled) by the low-pass 3 block. its characteristic is controlled by lubw (subaddress 09h, bit 4) to modify the width of the chrominance notch without influencing the chrominance path. the programmable frequency characteristics available, in conjunction with the lcbw2 to lcbw0 settings, can be seen in figs 13 to 16. it should be noted that these frequency curves are only valid for y-comb disabled filter mode (ycomb = 0). in comb filter mode the frequency response is flat. the centre frequency of the notch is automatically adapted to the chosen colour standard. the interpolated c b -c r samples are multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 2. this second dto is locked to the first subcarrier generator by an increment delay circuit matched to the processing delay, which is different for pal and ntsc standards according to the chosen comb filter algorithm. the two modulated signals are finally added to build the remodulated chrominance signal. the frequency characteristic of the separated luminance signal can be further modified by the succeeding luminance filter block. it can be configured as peaking (resolution enhancement) or low-pass block by lufi3 to lufi0 (subaddress 09h, bits 3 to 0). the 16 resulting frequency characteristics can be seen in fig.17. the lufi3 to lufi0 settings can be used as a user programmable sharpness control. the luminance filter block also contains the adjustable y-delay part; programmable by ydel2 to ydel0 (subaddress 11h, bits 2 to 0).
preliminary nda required con?dential - nda required page 33 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 mhb535 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) (5) (6) (7) (8) (1) (2) (3) (4) fig.13 transfer characteristics of the luminance notch filter in 3.58 mhz mode (y-comb filter disabled) at lubw = 0. (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
preliminary nda required con?dential - nda required page 34 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 mhb536 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) (5) (6) (7) (8) (1) (2) (3) (4) fig.14 transfer characteristics of the luminance notch filter in 3.58 mhz mode (y-comb filter disabled) at lubw = 1. (1) lcbw[2:0] = 000 (2) lcbw[2:0] = 010 (3) lcbw[2:0] = 100 (4) lcbw[2:0] = 110 (5) lcbw[2:0] = 001 (6) lcbw[2:0] = 011 (7) lcbw[2:0] = 101 (8) lcbw[2:0] = 111
preliminary nda required con?dential - nda required page 35 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 mhb537 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) (5) (6) (7) (8) (1) (2) (3) (4) fig.15 transfer characteristics of the luminance notch filter in 4.43 mhz mode (y-comb filter disabled) at lubw = 0. (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
preliminary nda required con?dential - nda required page 36 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 mhb538 - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) - 60 - 57 - 54 - 51 - 48 - 45 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0 v (db) f (mhz) (5) (6) (7) (8) (1) (2) (3) (4) fig.16 transfer characteristics of the luminance notch filter in 4.43 mhz mode (y-comb filter disabled) at lubw = 1. (1) lcbw[2:0] = 000. (2) lcbw[2:0] = 010. (3) lcbw[2:0] = 100. (4) lcbw[2:0] = 110. (5) lcbw[2:0] = 001. (6) lcbw[2:0] = 011. (7) lcbw[2:0] = 101. (8) lcbw[2:0] = 111.
preliminary nda required con?dential - nda required page 37 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 mhb539 - 1 0 1 2 3 4 5 6 7 8 9 v (db) v (db) f (mhz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 f (mhz) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 (8) (7) (6) (5) (4) (3) (2) (1) (9) (10) (11) (12) (13) (14) (15) (16) - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 3 fig.17 transfer characteristics of the luminance peaking/low-pass filter (sharpness). (1) lufi[3:0] = 0001. (2) lufi[3:0] = 0010. (3) lufi[3:0] = 0011. (4) lufi[3:0] = 0100. (5) lufi[3:0] = 0101. (6) lufi[3:0] = 0110. (7) lufi[3:0] = 0111. (8) lufi[3:0] = 0000. (9) lufi[3:0] = 1000. (10) lufi[3:0] = 1001. (11) lufi[3:0] = 1010. (12) lufi[3:0] = 1011. (13) lufi[3:0] = 1100. (14) lufi[3:0] = 1101. (15) lufi[3:0] = 1110. (16) lufi[3:0] = 1111.
preliminary nda required con?dential - nda required page 38 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.1.2.3 brightness contrast saturation (bcs) control and decoder output levels the resulting y (cvbs) and c b -c r signals are fed to the bcs block, which contains the following functions: chrominance saturation control by dsat7 to dsat0 luminance contrast and brightness control by dcon7 to dcon0 and dbri7 to dbri0 raw data (cvbs) gain and offset adjustment by rawg7 to rawg0 and rawo7 to rawo0 limiting y-c b -c r or cvbs to the values 1 (minimum) and 254 (maximum) to fulfil itu recommendation 601/656 . handbook, full pagewidth luminance 100% + 255 + 235 + 128 + 16 0 white black c b -component + 255 + 240 + 212 + 212 + 128 + 16 + 44 0 blue 100% blue 75% yellow 75% yellow 100% colourless c r -component + 255 + 240 + 128 + 16 + 44 0 red 100% red 75% cyan 75% cyan 100% colourless mhb730 fig.18 y-c b -c r range for scaler input and x-port output. itu recommendation 601/656 digital levels with default bcs (decoder) settings dcon[7:0] = 44h, dbri[7:0] = 80h and dsat[7:0] = 40h. equations for modification to the y-c b -c r levels via bcs control i 2 c-bus bytes dbri, dcon and dsat. luminance: chrominance: it should be noted that the resulting levels are limited to 1 to 254 in accordance with itu recommendation 601/656 . y out int dcon 68 ----------------- y 128 C () dbri + = c r c b () out int dsat 64 --------------- - c r c b , 128 C () 128 + = a. y output range. b. c b output range. c. c r output range.
preliminary nda required con?dential - nda required page 39 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.1.3 s ynchronization the prefiltered luminance signal is fed to the synchronization stage. its bandwidth is further reduced to 1 mhz in a low-pass filter. the sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. the resulting output signal is applied to the loop filter to accumulate all phase deviations. internal signals (e.g. hcl and hsy) are generated in accordance with analog front-end requirements. the loop filter signal drives an oscillator to generate the line frequency control signal lfco; see fig.20. the detection of pseudo syncs as part of the macrovision copy protection standard is also achieved within the synchronization circuit. the result is reported as flag copro within the decoder status byte at subaddress 1fh. 8.1.4 c lock generation circuit the internal cgc generates all clock signals required for the video input processor. the internal signal lfco is a digital-to-analog converted signal provided by the horizontal pll. it is the multiple of the line frequency: 6.75 mhz = 429 f h (50 hz), or 6.75 mhz = 432 f h (60 hz). fig.19 cvbs (raw data) range for scaler input, data slicer and x-port output. cvbs levels with default settings rawg[7:0] = 64 and rawo[7:0] = 128. equation for modification of the raw data levels via bytes rawg and rawo: it should be noted that the resulting levels are limited to 1 to 254 in accordance with itu recommendation 601/656 . cvbs out int rawg 64 ------------------ cvbs nom 128 C () rawo + = luminance + 255 + 209 + 71 + 60 1 white sync bottom black shoulder black sync luminance + 255 + 199 + 60 1 white sync bottom black shoulder = black sync mgd700 a. sources containing 7.5 ire black level offset (e.g. ntsc m). b. sources not containing black level offset.
preliminary nda required con?dential - nda required page 40 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 the lfco signal is multiplied by a factor of 2 and 4 in the internal pll circuit (including phase detector, loop filtering, vco and frequency divider) to obtain the output clock signals. the rectangular output clocks have a 50% duty factor. table 5 decoder clock frequencies clock frequency (mhz) xtalo 24.576 or 32.110 llc 27 llc2 13.5 llc4 (internal) 6.75 llc8 (virtual) 3.375 fig.20 block diagram of the clock generation circuit. band pass fc = llc/4 zero cross detection phase detection loop filter divider 1/2 divider 1/2 oscillator mhb330 llc2 llc lfco
preliminary nda required con?dential - nda required page 41 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.1.5 p ower - on reset and c hip e nable (ce) input a missing clock, insufficient digital or analog v dda0 supply voltages (below 2.8 v) will start the reset sequence; all outputs are forced to 3-state (see fig.21). the indicator output res is low for approximately 128 llc after the internal reset and can be applied to reset other circuits of the digital tv system. it is possible to force a reset by pulling the chip enable pin (ce) to ground. after the rising edge of ce and sufficient power supply voltage, the outputs llc, llc2 and sda return from 3-state to active, while the other signals have to be activated via programming. however, some external devices require an active clock during reset to avoid hang up. for these applications it is possible to activate both the i-port and/or the x-port outputs by pulling the itri- and/or xtri inputs to logic 1 by an external pull up resistor (4.7 k w ). in detail: pulling itri to 1 activates the outputs iclk, ipd[7:0], idq, igph, igpv, igp0 and igp1; pulling xtri to 1 activates the outputs xclk, xpd[7:0], xdq, xrh and xrv. during reset both iclk and xclck deliver the llc-clock (27 mhz) generated by the internal decoder pll. if itri and/or xtri are not connected, an internal pull up resistor takes care that these pins remain in 3-state. in any case it is possible to force these ports to 3-state by setting xpe[1:0] and/or ipe[1:0] to 00.
preliminary nda required con?dential - nda required page 42 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 fig.21 power-on control circuit. poc = power-on control. ce = chip enable input. xtalo = crystal oscillator output. llcint = internal system clock. resint = internal reset. llc = line-locked clock output, occurs also on pins xclk and/or iclk if enabled via pull up resistor on xtri and/or itri. res = reset output. mhb331 128 lcc 896 lcc digital delay some ms 20 to 200 m s pll-delay < 1 ms res (internal reset) llc resint llcint xtalo ce poc v dda poc logic analog poc v ddd digital poc delay clock pll ce llc clk0 resint res
preliminary nda required con?dential - nda required page 43 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.2 output formatter the output formatter of the decoder part contains the itu 656 8 bit / 10 bit formatter for the expansion port (x-port) data output (xpd[7:0], xrh, xrv) including the selection of the reference signals for the rt port (rtco, rts0 and rts1) and the expansion port (xrh, xrv and xdq) (for a detailed description see section 9.4.1) as well as the control circuitry for the signals needed for the internal paths to the scaler and data slicer part. this control circuitry requests decoded video data (y-c b -c r 4 : 2 : 2) or raw data from the comb?lter decoder output to be provided to expansion port (x-port) output, to the scaler input and to the vbi data slicer input. this data request is user controlled by the line control registers lcr2 to lcr24 (see also chapter 16; subaddresses 41h to 57h). each of the registers lcr2 to lcr23 defines a data type to be decoded in the associated line; i.e.: the vbi data type can be set independently for each of the lines. therefore lcr2 to lcr23 refer to line numbers. the selection in lcr24 values is valid for the rest of the corresponding field. the upper nibble of each of the 23 lcr registers contains the value for field 1 (odd), the lower nibble for field 2 (even). the relationship between lcr values and line numbers can be adjusted via voff8 to voff0, located in subaddresses 5bh (bit 4) and 5ah (bits 7 to 0), foff subaddress 5bh (bit d7) and vep subaddress 5bh (bit d5). the recommended values are voff[8:0] = 03h for 50 hz sources (with foff = 0) and voff[8:0] = 06h for 60 hz sources (with foff = 1), to accommodate line number conventions as used for pal, secam and ntsc standards; see tables 7 to 10. n ote : the line counting scheme for 60 hz standards, with voff = 0x06, as mentioned in fig.23, table 7 and table 8, leads the vbi slicer to take the old field id as reference for its field processing. for consistent id interpretation the voff value need to be set to 0x03. table 6 data formats at decoder output the adjustment of the slicer processing, the adjustment of video output data via the expansion port (x-port) and the adjustment of video data transferred to the scaler relative to the input signal source is defined by the programming data type 60hz / 525 lines vbi data standards 50hz / 625 lines vbi data standards no. binary description decoder output data format description decoder output data format 0 0000 do not acquire (active video) y-c b -c r 4:2:2 do not acquire (active video) y-c b -c r 4:2:2 1 0001 us teletext (wst525) raw data euro teletext (wst625) raw data 2 0010 nabts raw data euro teletext with progammable framing code raw data 3 0011 moji raw data reserved reserved 4 0100 us closed caption (cc525) raw data euro closed caption (cc625) raw data 5 0101 cgms (wss525) raw data euro wide screen signalling (wss625) raw data 6 0110 vitc525 raw data vitc625 raw data 7 0111 gemstar2x raw data vps raw data 8 1000 gemstar1x raw data reserved reserved 9 1001 reserved reserved reserved reserved 10 1010 open1 (5 mhz) raw data open1 (5 mhz) raw data 11 1011 open2 (5,7272 mhz) raw data open2 (5,7272 mhz) raw data 12 1100 reserved reserved reserved reserved 13 1101 do not acquire (raw) raw data do not acquire (raw) raw data 14 1110 do not acquire (test) reserved do not acquire (test) reserved 15 1111 do not acquire (active video) y-c b -c r 4:2:2 do not acquire (active video) y-c b -c r 4:2:2
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 44 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required registers 59h to 5bh, there are programmable offsets in the horizontal and vertical direction available: parameters hoff[10:0] 5bh[2:0] 59h[7:0], voff[8:0] 5bh[4] 5ah[7:0], foff[5bh[7]] and vep[5bh[5]]). i.e. these control registers are defining the decoder data output for mat - active video, raw samples (optionally a test line), which is delivered from combfilter video decoder output to the expansion port output, the sca ler and the vbi data slicer. table 7 relationship of lcr to line numbers in 525 lines/60 hz systems (part 1) vertical line offset, voff[8:0] = 06h,resp. 03h (subaddresses 5bh[4] and 5ah[7:0]); horizontal pixel offset, hoff[10:0] = 347h (subaddresses 5bh[ 2:0] and 59h[7:0]); foff = 1 (subaddress 5bh[7]), vep = 0 (subaddress 5bh[5]) table 8 relationship of lcr to line numbers in 525 lines/60 hz systems (part 2) vertical line offset, voff[8:0] = 06h,resp. 03h (subaddresses 5bh[4] and 5ah[7:0]); horizontal pixel offset, hoff[10:0] = 347h (subaddresses 5bh[ 2:0] and 59h[7:0]); foff = 1 (subaddress 5bh[7]), vep = 0 (subaddress 5bh[5]) line number (1st field) 521 522 523 524 525 1 2 3 4 5 6 7 8 9 active video equalization pulses serration pulses equalization pulses line number (2nd field) 259 260 261 262 263 264 265 266 267 268 269 270 271 272 active video equalization pulses serration pulses equalization pulses lcr voff = 06h 24 23456789 lcr voff = 03h 24 23456 line number (1st field) 10 11 12 18 19 20 21 22 23 24 25 26 27 28 nominal vbi-lines f1 active video line number (2nd field) 273 274 275 281 282 283 284 285 286 287 288 289 290 291 nominal vbi-lines f2 active video lcr voff = 06h 13 14 15 18 19 20 21 22 23 24 lcr voff = 03h 7 8 9 15 16 17 18 19 20 21 22 23 24
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 45 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required table 9 relationship of lcr to line numbers in 625 lines/50 hz systems (part 1) vertical line offset, voff[8:0] = 03h (subaddresses 5bh[4] and 5ah[7:0]); horizontal pixel offset, hoff[10:0] = 347h (subaddresses 5bh[2:0] and 59h[7:0]); foff = 0 (subaddress 5bh[7]), vep = 0 (subaddress 5bh[5]) table 10 relationship of lcr to line numbers in 625 lines/50 hz systems (part 2) vertical line offset, voff[8:0] = 03h (subaddresses 5bh[4] and 5ah[7:0]); horizontal pixel offset, hoff[10:0] = 347h (subaddresses 5bh[2:0] and 59h[7:0]); foff = 0 (subaddress 5bh[7]), vep = 0 (subaddress 5bh[5]) the relationship of these programming values to the input signal and the recommended values is outlined in table 7 to table 10. line number (1st field) 62162262362462512345 active video equalization pulses serration pulses equalization pulses line number (2nd field) 309 310 311 312 313 314 315 316 317 318 active video equalization pulses serration pulses equalization pulses lcr 24 2345 line number (1st field) 678910111213141516171819202122232425 nominal vbi-lines f1 active video line number (2nd field) 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 nominal vbi-lines f2 active video lcr 67891011121314151617181920212223 24
preliminary nda required con?dential - nda required page 46 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 fig.22 vertical timing diagram for 50 hz/625 line systems. (1) the inactive going edge of the v123 signal indicates whether the field is odd or even. if href is active during the falling edge of v123, the field is odd (field 1). if href is inactive during the falling edge of v123, the field is even. the specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. the control signals listed above are available on pins rts0, rts1, xrh and xrv according to the following table: for further information see section 16.2: tables 69, 70 and 71. name rts0 rts1 xrh xrv href x x x - f_itu656 --- x v123 x x - x vgate x x -- fid x x -- mhb540 vgate vsto [ 8:0 ] = 134h vsta [ 8:0 ] = 15h (a) 1st field cvbs itu counting single field counting 1 1 2 2 3 3 4 4 5 5 6 6 7 7 ... ... 22 22 625 312 624 311 623 310 622 309 23 23 fid href f_itu656 v123 (1) vgate cvbs itu counting single field counting fid href f_itu656 v123 (1) vsto [ 8:0 ] = 134h vsta [ 8:0 ] = 15h (b) 2nd field 313 313 314 1 315 2 316 3 317 4 318 5 319 6 ... ... 335 22 312 312 311 311 310 310 309 309 336 23
preliminary nda required con?dential - nda required page 47 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 fig.23 vertical timing diagram for 60 hz/525 line systems. (1) the inactive going edge of the v123 signal indicates whether the field is odd or even. if href is active during the falling edge of v123, the field is odd (field 1). if href is inactive during the falling edge of v123, the field is even. the specific position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. the control signals listed above are available on pins rts0, rts1, xrh and xrv according to the following table: for further information see section 16.2: tables 69, 70 and 71. name rts0 rts1 xrh xrv href x x x - f_itu656 --- x v123 x x - x vgate x x -- fid x x -- mhb541 vgate vsto [ 8:0 ] = 101h vsta [ 8:0 ] = 011h (a) 1st field cvbs itu counting single field counting 4 4 5 5 6 6 7 7 8 8 9 9 10 10 ... ... 21 21 3 3 2 2 1 1 525 262 22 22 fid href f_itu656 v123 (1) vgate cvbs itu counting single field counting fid href f_itu656 v123 (1) vsto [ 8:0 ] = 101h vsta [ 8:0 ] = 011h (b) 2nd field 266 3 267 4 268 5 269 6 270 7 271 8 272 9 ... ... 284 21 265 2 264 1 263 263 262 262 285 22
preliminary nda required con?dential - nda required page 48 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 fig.24 horizontal timing diagram (50/60 hz). the signals href, hs, cref2 and cref are available on pins rts0 and/or rts1. their polarity can be inverted via rtp0 and/or rtp1 (see section 16.2: tables 69, 70 and 71) the signals href and hs are available on pin xrh (see section 16.2 table 72). 108 - 107 107 - 106 mhb542 cvbs input 140 1/llc 5 2/llc expansion port data output 12 2/llc 720 2/llc 144 2/llc 138 2/llc 720 2/llc burst processing delay adc to expansion port: 0 0 2 2/llc 2 2/llc href (60 hz) hs (60 hz) sync clipped 16 2/llc 1 2/llc programming range (step size: 8/llc) programming range (step size: 8/llc) hs (50 hz) href (50 hz) cref cref2 cref cref2
preliminary nda required con?dential - nda required page 49 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.3 scaler the high performance video scaler in the SAA7115 has the following major blocks: acquisition control (horizontal and vertical timer) and task handling (the region/field/frame based processing) prescaler, for horizontal down-scaling by an integer factor, combined with appropriate band limiting filters, especially anti-aliasing for cif format brightness, saturation, contrast control to adjust scale dependent amplification line buffer, with asynchronous read and write, to support vertical up-scaling (e.g. for videophone application, converting 240 into 288 lines, y-c b -c r 4:2:2) vertical scaling, with phase accurate linear phase interpolation (lpi) for zoom and downscale, or phase accurate accumulation mode (acm) for large downscaling ratios and better alias suppression variable phase delay (vpd), operates as horizontal phase accurate interpolation for arbitrary non-integer scaling ratios, supporting conversion between square and rectangular pixel sampling output formatter for scaled y-c b -c r 4:2:2, y-c b -c r 4:1:1 and y only (format also for raw data) fifo, 32-bit wide, with 64 pixel capacity in y-c b -c r formats output interface, 8 or 16-bit (only if extended by h-port) data pins wide, synchronous or asynchronous operation, with stream events on discrete pins, or coded in the data stream. the overall h and v zooming (hv_zoom) is restricted by the input/output data rate relationships. with a safety margin of 2% for running in and running out, the maximum hv_zoom is equal to: for example: 1. input from decoder: 50 hz, 720 pixel, 288 lines, 16-bit data at 13.5 mhz data rate, 1 cycle per pixel; output: 8-bit data at 27 mhz, 2 cycles per pixel; the maximum hv_zoom is about: 2. input from x-port: 60 hz, 720 pixel, 240 lines, 8-bit data at 27 mhz data rate (itu 656), 2 cycles per pixel; output via i + h-port: 16-bit data at 27 mhz clock, 1 cycle per pixel; the maximum hv_zoom is about: the data flow in the scaler is controlled by internal data valid and data request flags (internal handshake signalling) between the sub-blocks, as the scaling process itself is discontinuous and dynamical. therefore the entire scaler acts as a pipeline buffer. depending on the actually programmed scaling parameters the effective buffer can exceed to an entire line. this allows vertical upscaling, more flexible video stream timing at the image port, discontinuous transfers and handshake. the access/bandwidth requirements to the vga frame buffer are reduced significantly. the video scaler receives its input signal from the video decoder or from the expansion port (x-port). it gets 16-bit y-c b -c r 4:2:2 input data at a continuous rate of 13.5 mhz from the decoder. discontinuous data stream can be accepted from the expansion port (x-port), normally 8-bit wide itu 656 like y-c b -c r data, accompanied by a pixel qualifier on xdq. the input data stream is sorted into two data paths, one for luminance (or raw samples) and one for time multiplexed chrominance c b and c r samples. an y-c b -c r 4 : 1 : 1 input format from the x-port is converted to 4 : 2 : 2 for the horizontal prescaling and vertical filter scaling operation. the scaler operation is defined by two programming pages a and b, representing two different tasks, that can be applied field alternating or to define two regions in a field (e.g. with different scaling range, factors and signal source during odd and even fields). each programming page contains control: 0.98 t_input_field t_v_blanking C in_pixel in_lines out_cycle_per_pix t_out_clk ------------------------------------------------------------------------------------------------------------------------------- ------ - 0.98 20 ms 24 64 m s C 720 288 2 37 ns -------------------------------------------------------- 1.18 = 0.98 16.666 ms 22 64 m s C 720 240 1 37 ns -------------------------------------------------------------- 2.34 =
preliminary nda required con?dential - nda required page 50 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 for signal source selection and formats for task handling and trigger conditions for input and output acquisition window definition for h-prescaler, v-scaler and h-phase scaling. raw vbi-data is handled as specific input format and needs its own programming page (equals own task). in vbi pass through operation the processing of prescaler and vertical scaling has to be set to no-processing, however, the horizontal fine scaling vpd can be activated. upscaling (oversampling, zooming), free of frequency folding, up to a factor of 3.5 can be achieved, as required by some software data slicing algorithms. these raw samples are transported through the image port as valid data and can be output as y only format. also this y only lines can be framed by sav and eav codes. 8.3.1 a cquisition control and task handling ( subaddresses 80h, 90h, 91h, 94h to 9fh and c4h to cfh) the acquisition control receives horizontal and vertical synchronization signals from the decoder section or from the x-port. the acquisition window is generated via pixel and line counters at the appropriate places in the data path. from x-port only qualified pixels and lines (lines with qualified pixel) are counted. the acquisition window parameters are as follows: signal source selection regarding input video stream and formats from the decoder, or from x-port (programming bits scsrc[1:0] 91h[5:4] and fsc[2:0] 91h[2:0]) remark : the input of raw vbi-data from the internal decoder need to be controlled via the decoder output formatter and the lcr registers (see section 8.2) vertical offset defined in lines of the video source, parameter yo[11:0] 99h[3:0] 98h[7:0] vertical length defined in lines of the video source, parameter ys[11:0] 9bh[3:0] 9ah[7:0] vertical length defined in number of target lines, as a result of vertical scaling, parameter yd[11:0] 9fh[3:0] 9eh[7:0] horizontal offset defined in number of pixels of the video source, parameter xo[11:0] 95h[3:0] 94h[7:0] horizontal length defined in number of pixels of the video source, parameter xs[11:0] 97h[3:0] 96h[7:0] horizontal destination size, defined in target pixels after fine scaling, parameter xd[11:0] 9dh[3:0] 9ch[7:0]. the source start offset (xo11 to xo0 and yo11 to yo0) opens the acquisition window, and the target size (xd11 to xd0, yd11 to yd0) closes the window, but the window is cut vertically, if there are less output lines than expected. the trigger events for the pixel and line counts are the horizontal and vertical reference edges as defined in subaddress 92h. the task handling is controlled by subaddress 80h and 90h (see section 8.3.1.2). to support instable non standard input signals, different operational modes are implemented (bits cmod and fmod). 8.3.1.1 input ?eld processing the scaler directly gets a corresponding field id information from the SAA7115 decoder path. if switched to the x-port, the trigger event for the field sequence detection from external signals (x-port) are defined in subaddress 92h. from the x-port the state of the scalers h-reference signal at the time of the v-reference edge is taken as field sequence identifier fid. for example, if the falling edge of the xrv input signal is the reference and the state of xrh input is logic 0 at that time, the detected field id is logic 0. the bits xfdv[92h[7]] and xfdh[92h[6]] define the detection event and state of the flag from the x-port. for the default setting of xfdv and xfdh at 00 the state of the h-input at the falling edge of the v-input is taken.
preliminary nda required con?dential - nda required page 51 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 the fid flag is used to determine whether the first or second field of a frame is going to be processed within the scaler and it is used as trigger condition for the task handling (see bits strc[1:0] 90h[1:0]). according to itu 656, when fid is at logic 0 means first field of a frame. to ease the application, the polarities of the detection results on the x-port signals and the internal decoder id can be changed via xfdh. as the v-sync from the decoder path has a half line timing (due to the interlaced video signal), but the scaler processing only knows about full lines, during 1st fields from the decoder the line count of the scaler possibly shifts by one line, compared to the 2nd field. this can be compensated for by switching the v-trigger event, as defined by xdv0, to the opposite v-sync edge or by using the vertical scalers phase offsets. the vertical timing of the decoder can be seen in figs 22 and 23. as the h and v reference events inside the itu 656 data stream (from x-port) and the real-time reference signals from the decoder path are processed differently, the trigger events for the input acquisition also have to be programmed differently. table 11 processing trigger and start 8.3.1.2 task handling the task handler controls the switching between the two programming register sets. the main function is controlled by subaddresses 90h and c0h. the operational modes of the task handler are controlled by the bits cmod[80h[7]] and fmod[9bh[7]]. a task is enabled via the global control bits tea[80h[4]] and teb[80h[5]]. the handler is then triggered by events, which can be defined for each register set. in case of a programming error the task handling and the complete scaler can be reset to the initial states by setting the software reset bit swrst[88h[5]] to logic 0. especially if the programming registers, related acquisition window and scale are reprogrammed while a task is active, a software reset must be performed after programming. contrary to the disabling/enabling of a task, which is evaluated at the end of a running task, when swrst is at logic 0 it sets the internal state machines directly to their idle states. the basic operation of the task handler is strongly orientated on the window definitions, which means, if a starting point (in terms of xo and yo values) is missed, or the window definition (especially in terms of the (yo + ys) value) is larger than the input field, the operation is inhibited or incoming video fields are skipped. to better support non standard input signals and signal sources with varying field lengths (like a vcr in fast forward/rewind mode), there are now some different operational modes implemented for the task handling. field mode (bit fmod [9bh[7]]) this is a task specific bit (for flexibility reasons), but normally both tasks should be programmed to the same value. if the fmod bit is set to 1 the yo and ys parameters change the meaning. yo defines the start line and ys the end line (instead of the window length) for the scalers processing window. additionally the trigger conditions of the task handler are changed. description xdv1 92h[5] xdv0 92h[4] xdh 92h[2] internal decoder : the processing triggers at the reference edge of the v123 pulse (see figs 22 (50 hz) and 23 (60 hz)), and starts earliest with the rising edge of the decoder href at line number: falling edge: 4/7 (50/60 hz, 1st field), resp. 3/6 (50/60 hz, 2nd field) (decoder count) 0 1 0 rising edge: 2/5 (50/60 hz, 1st field), resp. 2/5 (50/60 hz, 2nd field) (decoder count) 0 0 0 external itu 656 stream : the processing starts earliest with sav at line number 23 (50 hz system), respectively line 20 (60 hz system) (according to itu 656 count) 000
preliminary nda required con?dential - nda required page 52 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 in field mode the vertical trigger event gets higher priority than the vertical window definition. the processing is normally started at line number yo and ends at line number ys, but - if a vertical trigger occurs, before the line number ys is reached, the field processing is terminated and the next task is checked - if the actual line count at v-trigger is between the yo and the ys value, the task processing is started, also if the line number yo is missed. continuous mode (bit cmod [80h[7]]) applications, which do not use the vertical scaling, may take advantage from the continuous processing mode. in this mode a task is started via the swrst bit and the task enable bits tea or teb. the horizontal window definition keeps its meaning, but yo and ys are ignored. the vertical blanking scheme is defined by the selected v-sync (see bits v_eav). once started, the vertical retrigger pulses from the input are ignored and swrst at 0 is needed to stop the task processing. start, repeat and skip the start condition for the handler is defined by bits strc[1:0] 90h[1:0] and means: start immediately, wait for next v-sync, next fid at logic 0 or next fid at logic 1. the fid is evaluated, if the vertical and horizontal offsets are reached. when rptsk[90h[2]] is at logic 1 the actual running task is repeated (under the defined trigger conditions), before handing control over to the alternate task. to support field rate reduction, the handler is also enabled to skip fields (bits fskp[2:0] 90h[5:3]) before executing the task. a toggle flag is generated (used for the correct output field processing), which changes state at the beginning of a task, every time a task is activated. examples are given in section 8.3.1.3. remarks: to activate a task the start condition must be fulfilled and, in case of fmod = 0, the acquisition window offsets must be reached . for example, in case of start immediately, and two regions are defined for one field, the offset of the lower region must be greater than (offset + length) the upper region, if not, the actual counted h and v position at the end of the upper task is beyond the programmed offsets and the processing will wait for next v. basically the trigger conditions are checked, when a task is activated . it is important to realize, that they are not checked while a task is inactive. so you can not trigger to next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task a strc[2:0] = 2, yo[11:0] = 310 and task b strc[2:0] = 3, yo[11:0] = 310 results in output field rate of 50 3 hz). after power-on or software reset (via swrst[88h[5]]) task b gets priority over task a . 8.3.1.3 output ?eld processing as a reference for the output field processing, two signals are available for the back-end hardware. these signals are the input field id from the scaler source and a toogle flag, which shows that an active task is used an odd (1, 3, 5...) or even (2, 4, 6...) number of times. using a single or both tasks and reducing the field or frame rate with the task handling functionality, the toggle information can be used, to reconstruct an interlaced scaled picture at a reduced frame rate. the toggle flag isnt synchronized to the input field detection, as it is only dependent on the interpretation of this information by the external hardware, whether the output of the scaler is processed correctly (see section 8.3.3). with ofidc = 0, the scalers input field id is available as output field id on bit d6 of sav and eav, respectively on pin igp0 (igp1), if fid output is selected. when ofidc[90h[6]] = 1, the toggle information is available as output field id on bit d6 of sav and eav, respectively on pin igp0 (igp1), if fid output is selected.
preliminary nda required con?dential - nda required page 53 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 additionally the bit d7 of sav and eav can be defined via conlh[90h[7]]. conlh[90h[7]] = 0 (default) sets d7 to logic 1, a logic 1 inverts the sav/eav bit d7. so it is possible to mark the output of the both tasks by different sav/eav codes. this bit can also be seen as task flag on the pins igp0 (igp1), if task output is selected.
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 54 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required table 12 examples for ?eld processing notes 1. single task every field; ofidc = 0; subaddress 90h at 40h; teb[80h[5]] = 0. 2. tasks are used to scale to different output windows, priority on task b after swrst. 3. both tasks at 1 2 frame rate; ofidc = 0; subaddresses 90h at 43h and c0h at 42h. 4. in examples 3 and 4 ofidc = 1, thus the association between input fid and tasks may be flipped, dependent on which time the swrst is deasserted. 5. task b at 2 3 frame rate constructed from neighbouring motion phases; task a at 1 3 frame rate of equidistant motion phases; subaddresses 90h at 41h and c0h at 45h. 6. task a and b at 1 3 frame rate of equidistant motion phases; subaddresses 90h at 41h and c0h at 49h. 7. due to no data output for this field, the state of the prior field is hold. 8. it is assumed that input/output fid = 0 (= upper lines); up = upper lines; lo = lower lines. 9. o = data output; no = no output. subject example 1 (1) example 2 (2)(3) example 3 (2)(4)(5) example 4 (2)(4)(6) field sequence frame/field 1/1 1/2 2/1 1/1 1/2 2/1 2/2 1/1 1/2 2/1 2/2 3/1 3/2 1/1 1/2 2/1 2/2 3/1 3/2 processed by task a a a b a b a b b a b b a b b a b b a state of detected itu 656 fid 0 1 00101010101 0 10 1 01 toggle ?ag 1 0 1 1 1 0 0 1 0 1 1 0 0 0 (7) 111 (7) 00 bit d6 of sav/eav byte 0 1 0 0 1 0 1 1 0 1 1 0 0 0 (7) 111 (7) 00 required sequence conversion at the vertical scaler (8) up up lo lo up up up up lo lo up up lo lo up lo lo up up lo lo lo up up lo up up up lo lo up lo lo lo up up lo up output (9) o o ooooooooooonooonooo
preliminary nda required con?dential - nda required page 55 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.3.2 h orizontal scaling the overall horizontal required scaling factor has to be split into a binary and a rational value according to the equation: with there is where the parameter of prescaler xpsc[5:0] = 1 to 63 and the parameter of vpd phase interpolation xscy[12:0] = 300 to 8191 (0 to 299 are only theoretical values). for example, 1 3.5 is to split in 1 4 1.14286. the binary factor is processed by the prescaler, the arbitrary non-integer ratio is achieved via the variable phase delay vpd circuitry, called horizontal fine scaling. the latter calculates horizontally interpolated new samples with a 6-bit phase accuracy, which relates to less than 1 ns jitter for regular sampling scheme. prescaler and fine scaler create the horizontal scaler of the SAA71157115. using the accumulation length function of the prescaler (xacl[5:0] a1h[5:0]), application and destination dependent (e.g. scale for display or for a compression machine), a compromise between visible bandwidth and alias suppression can be determined. 8.3.2.1 horizontal prescaler (subaddresses a0h to a7h and d0h to d7h) the prescaling function consists of an fir anti-alias filter stage and an integer prescaler, which creates an adaptive prescale dependent low-pass filter to balance sharpness and aliasing effects. the fir prefilter stage implements different low-pass characteristics to reduce alias for downscales in the range of 1to 1 2 . a cif optimized filter is built-in, which reduces artefacts for cif output formats (to be used in combination with the prescaler set to 1 2 scale); see table 13. fade-in and fade-out of the filters is achieved by copying an original source sample each as first and last pixel after prescaling. figs 25 and 26 show the frequency characteristics of the selectable fir filters. table 13 fir pre?lter functions the function of the prescaler is defined by: an integer prescaling ratio xpsc[5:0] a0h[5:0] (equals 1 to 63), which covers the integer downscale range 1 to 1 63 an averaging sequence length xacl[5:0] a1h[5:0] (equals 0 to 63); range 1 to 64 a dc gain renormalization xdcg[2:0] a2h[2:0]; 1 down to 1 128 the bit xc2_1[a2h[3]], which defines the weighting of the incoming pixels during the averaging process: C xc2_1 = 0 t 1 + 1...+ 1 +1 C xc2_1 = 1 t 1 + 2...+ 2 +1 the prescaler creates a prescale dependent fir low-pass, with up to (64 + 7) filter taps. the parameter xacl[5:0] can be used to vary the low-pass characteristic for a given integer prescale of 1 xpsc[5:0] . the user can therewith decide between signal bandwidth (sharpness impression) and alias. pfuv[1:0] a2h[7:6] pfy[1:0] a2h[5:4] luminance filter coefficients chrominance coefficients 00 bypassed bypassed 01 121 121 10 - 1 1 1.75 4.5 1.75 1 - 1 381083 11 12221 12221 h-scale ratio output pixel input pixel ------------------------------ = h-scale ratio 1 xpsc[5:0] --------------------------- - 1024 xscy[12:0] ------------------------------ - =
preliminary nda required con?dential - nda required page 56 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 remark : due to bandwidth considerations xpsc[5:0] and xacl[5:0] can be chosen different to the mentioned equations or table 14, as the h-phase scaling is able to scale in the range from zooming up by factor 3 to downscale by a factor of 1024 8191 . equation for xpsc[5:0] calculation is: where, the range is 1 to 63 ( value 0 is not allowed ); npix_in = number of input pixel, and npix_out = number of desired output pixel over the complete horizontal scaler. the use of the prescaler results in a xacl[5:0] and xc2_1 dependent gain amplification. the amplification can be calculated according to the equation: dc gain = (xc2_1 + 1) xacl[5:0] + (1 - xc2_1). it is recommended to use sequence lengths and weights, which results in a dc gain amplification of 2 n , as these amplitudes can be renormalized by the xdcg[2:0] controlled shifter of the prescaler. other amplifications have to be normalized by using the following bcs control circuitry according to the equation: where: 2 xdcg[2:0] 3 dc gain in these cases the prescaler has to be set to an overall gain of 1, e.g. for an accumulation sequence of 1 + 1 + 1 (xacl[5:0] = 2 and xc2_1 = 0), xdcg[2:0] must be set to 010, this equals 1 4 and the bcs has to amplify the signal to 4 3 (satn[7:0] and cont[7:0] value = lower integer of 4 3 64). the use of xacl[5:0] is xpsc[5:0] dependent. xacl[5:0] must be < 2 xpsc[5:0]. xacl[5:0] can be used to find a compromise between bandwidth (sharpness) and alias effects. figs 27 and 28 show some resulting frequency characteristics of the prescaler. table 14 shows the recommended prescaler programming. other programming settings, than given in table 14, may result in better alias suppression, but the resulting dc gain amplification needs to be compensated by the bcs control for example, if xacl[5:0] = 5, xc2_1 = 1, then the dc gain = 10 and the required xdcg[2:0] = 4. the horizontal source acquisition timing and the prescaling ratio is identical for both the luminance path and chrominance path, but the fir filter settings can be defined differently in the two channels. xpsc[5:0] lower integer of npix_in npix_out ----------------------- = 1 2 n ------ cont[7:0] satn[7:0] lower integer of 2 xdcg[2:0] dc gain 64 ---------------------------------- ==
preliminary nda required con?dential - nda required page 57 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 mhb543 v (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 f_sig/f_clock (1) (2) (3) - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 6 3 fig.25 luminance prefilter characteristic. (1) pfy[1:0] = 01. (2) pfy[1:0] = 10. (3) pfy[1:0] = 11. mhb544 v (db) 0 0.025 0.05 0.075 0.1 0.125 0.15 0.175 0.2 0.225 0.25 f_sig/f_clock (1) (2) (3) - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 6 3 fig.26 chrominance prefilter characteristic. (1) pfuv[1:0] = 01. (2) pfuv[1:0] = 10. (3) pfuv[1:0] = 11.
preliminary nda required con?dential - nda required page 58 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 xc2_1 = 0; zeros at with xacl = (1), (2), (3), (4) or (5) fn 1 xacl 1 + ------------------------ - = mhb545 v (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 (1) (2) (3) (4) (5) f_sig/f_clock - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 6 3 fig.27 examples for prescaler filter characteristics: effect of increasing xacl[5:0]. fig.28 examples for prescaler filter characteristics: setting xc2_1 =1. (1) xc2_1 = 0 and xacl[5:0] = 1. (2) xc2_1 = 1 and xacl[5:0] = 2. (3) xc2_1 = 0 and xacl[5:0] = 3. (4) xc2_1 = 1 and xacl[5:0] = 4. (5) xc2_1 = 0 and xacl[5:0] = 7. (6) xc2_1 = 1 and xacl[5:0] = 8. mhb546 - 42 - 39 - 36 - 33 - 30 - 27 - 24 - 21 - 18 - 15 - 12 - 9 - 6 - 3 0 6 3 v (db) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 f_sig/f_clock (1) (2) (3) (4) (5) (6) 3 db at 0.25 6 db at 0.33
preliminary nda required con?dential - nda required page 59 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 14 xacl[5:0] example of usage note 1. resulting fir function. prescale ratio xpsc [5:0] recommended values fir prefilter pfy (p b -p r ) for lower bandwidth requirements for higher bandwidth requirements xacl[5:0] xc2_1 xdcg[2:0] xacl[5:0] xc2_1 xdcg[2:0] 110 0 0 0 0 0 0to2 1 22 2 1 2 1 0 1 0to2 (121) 1 4 (1) (1 1) 1 2 (1) 1 33 4 1 3 3 0 2 2 (12221) 1 8 (1) (1111) 1 4 (1) 1 44 7 0 3 4 1 3 2 (11111111) 1 8 (1) (1 2 2 2 1) 1 8 (1) 1 55 8 1 4 7 0 3 2 (122222221) 1 16 (1) (11111111) 1 8 (1) 1 66 8 1 4 7 0 3 3 (122222221) 1 16 (1) (11111111) 1 8 (1) 1 77 8 1 4 7 0 3 3 (122222221) 1 16 (1) (11111111) 1 8 (1) 1 88 15 0 4 8 1 4 3 (1111111111111111) 1 16 (1) (122222221) 1 16 (1) 1 99 15 0 4 8 1 4 3 (1111111111111111) 1 16 (1) (122222221) 1 16 (1) 1 10 10 16 1 5 8 1 4 3 (12222222222222221) 1 32 ( 1) (122222221) 1 16 (1) 1 13 13 16 1 5 16 1 5 3 1 15 15 31 0 5 16 1 5 3 1 16 16 32 1 6 16 1 5 3 1 19 19 32 1 6 32 1 6 3 1 31 31 32 1 6 32 1 6 3 1 32 32 63 1 7 32 1 6 3 1 35 35 63 1 7 63 1 7 3
preliminary nda required con?dential - nda required page 60 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.3.2.2 horizontal ?ne scaling (variable phase delay ?lter; subaddresses a8h to afh and d8h to dfh) the horizontal fine scaling (vpd) should operate at scaling ratios between 1 2 and 2 (0.8 and 1.6), but can also be used for direct scaling in the range from 1 7.999 to (theoretical) zoom 3.5 (restriction due to the internal data path architecture), without prescaler. in combination with the prescaler a compromise between sharpness impression and alias can be found, which is signal source and application dependent. for the luminance channel a filter structure with 10 taps is implemented, and for the chrominance a filter with 4 taps. luminance and chrominance scale increments (xscy[12:0] a9h[4:0]a8h[7:0] and xscc[12:0] adh[4:0]ach[7:0]) are defined independently, but must be set in a 2 : 1 relationship in the actual data path implementation. the phase offsets xphy[7:0] aah[7:0] and xphc[7:0] aeh[7:0] can be used to shift the sample phases slightly. xphy[7:0] and xphc[7:0] covers the phase offset range 7.999t to 1 32 t. the phase offsets should also be programmed in a 2 : 1 ratio. the underlying phase controlling dto has a 13-bit resolution. according to the equations and the vpd covers the scale range from 0.125 to zoom 3.5. vpd acts equivalent to a polyphase filter with 64 possible phases. in combination with the prescaler, it is possible to get very accurate samples from a highly anti-aliased integer downscaled input picture. 8.3.3 v ertical scaling the vertical scaler of the SAA7115 consists of a line fifo buffer for line repetition and the vertical scaler block, which implements the vertical scaling on the input data stream in 2 different operational modes from theoretical zoom by 64 down to icon size 1 64 . the vertical scaler is located between the bcs and horizontal fine scaler, so that the bcs can be used to compensate the dc gain amplification of the acm mode (see section 8.3.3.2) as the internal rams are only 8-bit wide. 8.3.3.1 line fifo buffer (subaddresses 91h, b4h and c1h, e4h) the line fifo buffer is a dual ported ram structure for 768 pixels, with asynchronous write and read access. the line buffer can be used for various functions, but not all functions may be available simultaneously. the line buffer can buffer a complete unscaled active video line or more than one shorter lines (only for non-mirror mode), for selective repetition for vertical zoom-up. for zooming up 240 lines to 288 lines e.g., every fourth line is requested (read) twice from the vertical scaling circuitry for calculation. for conversion of a 4:2:0or4:1:0 input sampling scheme (mpeg, video phone, indeo yuv-9) to itu like sampling scheme 4 : 2 : 2, the chrominance line buffer is read twice or four times, before being refilled again by the source. it has to be preserved by means of the input acquisition window definition, so that the processing starts with a line containing luminance and chrominance information for 4:2:0 and 4:1:0 input. the bits fsc[2:1] 91h[2:1] define the distance between the y/c lines. in the case of 4:2:2 and 4:1:1 fsc2 and fsc1 have to be set to 00. the line buffer can also be used for mirroring, i.e. for flipping the image left to right, for the vanity picture in video phone applications (bit ymir[b4h[4]]). in mirror mode only one active prescaled line can be held in the fifo at a time. the line buffer can be utilized as an excessive pipeline buffer for discontinuous and variable rate transfer conditions at the expansion port or image port. remark to 4 : x : 0 input from x-port : these input streams need to look like regular 4:2:2 input and are formatted to the internal 16 bit yuv format. at its input port the line fifo only ignores 1 of 2, resp. 3 of 4 chrominance lines, where fsc defines the skipping sequence. xscy[12:0] 1024 npix_in xpsc[5:0] --------------------------- - 1 npix_out ----------------------- = xscc[12:0] xscy[12:0] 2 ------------------------------ - =
preliminary nda required con?dential - nda required page 61 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.3.3.2 vertical scaler (subaddresses b0h to bfh and e0h to efh) vertical scaling of any ratio from 64 (theoretical zoom) to 1 63 (icon) can be applied. the vertical scaling block consists of another line delay, and the vertical filter structure, that can operate in two different modes; linear phase interpolation (lpi) and accumulation (acm) mode. these are controlled by ymode[b4h[0]]: lpi mode : in lpi mode (ymode = 0) two neighbouring lines of the source video stream are added together, but weighted by factors corresponding to the vertical position (phase) of the target output line relative to the source lines. this linear interpolation has a 6-bit phase resolution, which equals 64 intra line phases. it interpolates between two consecutive input lines only. lpi mode should be applied for scaling ratios around 1 (down to 1 2 ), it must be applied for vertical zooming . acm mode : the vertical accumulation (acm) mode (ymode = 1) represents a vertical averaging window over multiple lines, sliding over the field. this mode also generates phase correct output lines. the averaging window length corresponds to the scaling ratio, resulting in an adaptive vertical low-pass effect, to greatly reduce aliasing artefacts. acm can be applied for downscales only from ratio 1 down to 1 64 . acm results in a scale dependent dc gain amplification , which has to be precorrected by the bcs control of the scaler part. the phase and scale controlling dto calculates in 16-bit resolution, controlled by parameters yscy[15:0] b1h[7:0] b0h[7:0] and yscc[15:0] b3h[7:0] b2h[7:0], continuously over the entire filed. a start offset can be applied to the phase processing by means of the parameters ypy3[7:0] to ypy0[7:0] in bfh[7:0] to bch[7:0] and ypc3[7:0] to ypc0[7:0] in bbh[7:0] to b8h[7:0]. the start phase covers the range of 255 32 to 1 32 lines offset. by programming appropriate, opposite, vertical start phase values (subaddresses b8h to bfh and e8h to efh) depending on odd/even field id of the source video stream and a/b-page cycle, frame id conversion and field rate conversion are supported (i.e. de-interlacing, re-interlacing). figs 29 and 30 and tables 15 and 16 describe the use of the offsets. remark: the vertical start phase, as well as scaling ratio are defined independently for luminance and chrominance channel, but must be set to the same values in the actual implementation for accurate 4 :2:2 output processing. the vertical processing communicates on its input side with the line fifo buffer. the scale related equations are: scaling increment calculation for acm and lpi mode, downscale and zoom: yscy[15:0] and yscc[15:0] bcs value to compensate dc gain in acm mode (contrast and saturation have to be set): cont[7:0] a5h[7:0] respectively satn[7:0] a6h[7:0] , or 8.3.3.3 use of the vertical phase offsets as described in section 8.3.1.3, the scaler processing may run randomly over the interlaced input sequence (see parameters strc[1:0], fskp[2:0] and rptsk). additionally the interpretation and timing between itu 656 field id and real-time detection by means of the state of h-sync at the falling edge of v-sync may result in different field id interpretation. a vertically scaled interlaced output also gets a larger vertical sampling phase error, if the interlaced input fields are processed, without regard to the actual scale at the starting point of operation (see fig.29). for correct interlaced processing the vertical scaler must be used with respect to the interlace properties of the input signal and, if required, for conversion of the field sequences. lower integer of = 1024 nline_in nline_out ------------------------ - ? ?? lower integer of nline_out nline_in ------------------------ - 64 ? ?? = lower integer of 1024 yscy[15:0] ------------------------------ - 64 ? ?? =
preliminary nda required con?dential - nda required page 62 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 four events should be considered, they are illustrated in fig.30. mhb547 mismatched vertical line distances scale dependent start offset correct scale dependent position unscaled input scaled output, no phase offset scaled output, with phase offset ?ld 1 ?ld 2 ?ld 1 ?ld 2 ?ld 1 ?ld 2 fig.29 basic problem of interlaced vertical scaling (example: downscale 3 5 ). ?eld 1 ?eld 2 ?eld 1 ?eld 2 ?eld 1 ?eld 2 case up-up case lo-lo case up-lo case lo-up upper lower a b c d a = 1/2 input line shift = 16 b = 1/2 input line shift +1/2 scale increment = yscy/64 + 16 c = 1/2 scale increment= yscy / 64 d = no offset = 0 example: interlace vertical scaling down to 3 / 5, with ?eld conversion note: offset = 1024 / 32 = 32 = 1 line shift fig.30 derivation of the phase related equations r = reference position for upper output ?eld r
preliminary nda required con?dential - nda required page 63 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 in tables 15 and 16 pho is a usable common phase offset. it should be noted that the equations of fig.30 produce an interpolated output, also for the unscaled case, as the geometrical reference position ( r ) for all conversions is the position of the first line of the lower field (see table 15). if there is no need for up-lo and lo-up conversion and the input field id is the reference for the back-end operation, then it is up-lo = up-up and lo-up = lo-lo and the 1 2 line phase shift (pho + 16) can be skipped. this case is listed in table 16. the SAA7115 supports 4 phase offset registers per task and component (luminance and chrominance). the value of 20h represents a phase shift of one line. the registers are assigned to the following events; e.g. subaddresses b8h to bbh: b8h: 00 = input field id 0, task status bit 0 (toggle status, see section 8.3.1.3) b9h: 01 = input field id 0, task status bit 1 bah: 10 = input field id 1, task status bit 0 bbh: 11 = input field id 1, task status bit 1. depending on the input signal (interlaced or non-interlaced) and the task processing 50 hz or field reduced processing with one or two tasks (see examples in section 8.3.1.3), other combinations may also be possible, but the basic equations are the same. table 15 examples for vertical phase offset usage: global equations (referring to reference position r) table 16 vertical phase offset usage; assignment of the phase offsets for ofidc[90[6]] = 0, scaler input field id as output id notes 1. referring to the upper input field as reference position, a value of 16 is to be substracted from the global equations of table 15. input field under processing output field interpretation used abbreviation equation for phase offset calculation (decimal values) upper input lines upper output lines up-up pho + 16 upper input lines lower output lines up-lo lower input lines upper output lines lo-up pho lower input lines lower output lines lo-lo assumed backend interprets output field id at 0 as upper output lines detected input field id task status bit vertical phase offset equation to be used (values) 0 = upper lines 0 ypy(c)0 up-up (pho) 0 = upper lines 1 ypy(c)1 up-up (pho) 1 = lower lines 0 ypy(c)2 lo-lo (pho + yscy / 64 - 16) 1 = lower lines 1 ypy(c)3 lo-lo (pho + yscy / 64 - 16) pho yscy[15:0] 64 ------------------------------ - 16 ++ pho yscy[15:0] 64 ------------------------------ - +
preliminary nda required con?dential - nda required page 64 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 17 vertical phase offset usage: assignment of the phase offsets for ofidc[90[6]] = 1 detected input field id task status bit vertical phase offset backend interprets output field id 0 as upper lines; equation to be used backend interprets output field id 1 as upper lines; equation to be used 0 = upper lines 0 ypy(c)0 up-up up-lo 0 = upper lines 1 ypy(c)1 up-lo up-up 1 = lower lines 0 ypy(c)2 lo-up lo-lo 1 = lower lines 1 ypy(c)3 lo-lo lo-up
preliminary nda required con?dential - nda required page 65 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.4 vbi-data decoder and capture (subaddresses 40h to 7fh) the SAA7115 contains a versatile vbi-data decoder and the option of reading back sliced vbi data for low bitrate standards. 8.4.1 vbi d ata s licer the circuitry recovers the actual clock phase during the clock run-in period, slices the data bits with the selected data rate, and groups them into bytes. the result is buffered into a dedicated vbi-data fifo with a capacity of 2 56 bytes (2 14 dwords). the vbi data slicing is controlled by the programming registers 40h to 5dh. register 40h and 58h are controlling the slicing process itself. the line control registers (lcr registers) 41h to 57h are defining the data type (vbi data standard) to be decoded. the data type is specified on a line by line basis for the lines two to 23 separately for even and odd field and depends additionally on the detected video standard (i.e. whether the incoming video is a 50hz / 625 lines or 60hz / 525 lines signal). the definition for line control register lcr24 is valid for the rest of the corresponding field, normally no text data (video data) should be selected there (lcr24_[7:0] = ffh) to stop the activity of the vbi-data slicer during active video. the supported vbi-data standards are shown in table 18 for 60hz / 525 lines signals and 19 for 50hz / 625 lines signals. table 18 60hz / 525 lines vbi data types supported by the data slicer block data type 60hz / 525 lines vbi data standards no. binary description data rate (mbits/s) framing code framing code window hamming check decoder output data format 0 0000 do not acquire (active video) - - - - y-c b -c r 4:2:2 1 0001 us teletext (wst525) 5.7272 0x27 wst525 always raw data 2 0010 nabts 5.7272 programmable nabts optional raw data 3 0011 moji 5.7272 programmable (1) 1. should be set to 0x47 for moji moji - raw data 4 0100 us closed caption (cc525, line21) 0.503 001 binary cc525 - raw data 5 0101 us wide screen signalling (wss525, cgms) 0.447443 10 binary wss525 - raw data 6 0110 vitc525 1.7898 10 binary vitc525 - raw data 7 0111 gemstar2x 1.007 0x4ed 4ed h - raw data 8 1000 gemstar1x 0.503 001 binary - raw data 9 1001 reserved - - - - reserved 10 1010 open1 (5 mhz) 5 programmable 8-16us - raw data 11 1011 open2 (5,7272 mhz) 5.7272 programmable 8-16us - raw data 12 1100 reserved - - - - reserved 13 1101 do not acquire (raw) - - - - raw data 14 1110 do not acquire (test) - - - - reserved 15 1111 do not acquire (active video) - - - - y-c b -c r 4:2:2
preliminary nda required con?dential - nda required page 66 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 19 50hz / 625 lines vbi data types supported by the data slicer block the adjustment of the slicer processing to the input signal source is defined by the programming registers 59h to 5bh, there are programmable offsets in the horizontal and vertical direction available: parameters hoff[10:0] 5bh[2:0] 59h[7:0], voff[8:0] 5bh[4] 5ah[7:0], foff[5bh[7]] and vep[5bh[5]]). contrary to the scaler counting scheme, the slicer offsets define the position of the h and v trigger events related to the processed video field. the trigger events are the falling edge of href and the falling or rising edge of v123 (defined by vep[5bh[5]]) from the decoder processing part. note : the field id, used for the slicers data packing, is taken at the internal pixel 1 and line 1 position. hence for correct line counting according itu656 and for 60 hz input signals (see fig.23), the old value of the field id is taken as id reference. this has effect on the i2c read back registers, on the lcr table, the lcr controlled field id generation and the internal header information of the slicers output stream. for consistent id interpretation, the vertical offset parameter voff for ntsc has to be set to 0x03. for this case the lcr table covers the range from line 5 to 27 and line 21 corresponds to lcr18. the relationship of these programming values to the input signal and the recommended values is outlined in table 7 to table 10. the register sldmod[4:0] 5dh[4:0] defines the slicer data output mode at the i-port of the SAA7115. this register enables the vbi output and defines the mode of data insertion into the i-port data stream. status information can be read form register 5eh. data type 50hz / 625 lines vbi data standards no. binary description data rate (mbits/s) framing code framing code window hamming check decoder output data format 0 0000 do not acquire (active video) - - - - y-c b -c r 4:2:2 1 0001 european teletext (wst625), chinese teletext (ccst625) 6.9375 0x27 wst625 always raw data 2 0010 euro teletext with progammable framing code 6.9375 programma ble gen_text optional raw data 3 0011 reserved - - - - raw data 4 0100 euro closed caption (cc625) 0.500 001 binary cc625 - raw data 5 0101 euro wide screen signalling (wss625) 5 0x1e3c1f wss625 - raw data 6 0110 vitc625 1.8125 10 binary vitc625 - raw data 7 0111 vps 5 0x9951 vps - raw data 8 1000 reserved - - - - raw data 9 1001 reserved - - - - reserved 10 1010 open1 (5 mhz) 5 programma ble 8-16us - raw data 11 1011 open2 (5,7272 mhz) 5.7272 programma ble 8-16us - raw data 12 1100 reserved - - - - reserved 13 1101 do not acquire (raw) - - - - raw data 14 1110 do not acquire (test) - - - - reserved 15 1111 do not acquire (active video) - - - - y-c b -c r 4:2:2
preliminary nda required con?dential - nda required page 67 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.4.2 i 2 cr eadback of sliced vbi data the i 2 c readback unit offers readback for the following vbi data standards via the i 2 c bus (subaddresses 66h 7fh): 60hz / 525 lines vbi data standards C us closed caption (cc525): 1 byte header + 2 x 2 bytes payload C copy generation management system (cgms, us wide screen signalling (wss525)): 1 byte header + 2 x 3 bytes payload C gemstar1x: 1 byte header + 2 x 2 bytes payload C gemstar2x: 1 byte header + 2 x 4 bytes payload 50hz / 625 lines vbi data standards C european closed caption (cc625): 1 byte header + 2 x 2 bytes payload C european wide screen signalling (wss625, majority decoded and be-phase decoded): 1 byte header + 2 x 2 bytes payload for each vbi data standard the amount of data of one frame (one line per field) and a one byte header can be stored. the i2c readback registers for wide screen signalling and closed caption are shared for 60hz / 525 lines vbi data standards and 50hz / 625 lines vbi data standards. in case of decoding wss625 this data is sore to the same registers than decoded wss525 data with the third payload byte of each line left unconsidered. the one byte header delivers decoding error status and the current update status separately for each field as well as a free running 4 bit field counter as reference information, to be able to detect multiple read data or loss of data (refer to table 20) table 20 structure of the i 2 c readback header the i2c readback unit guarantees consistency between header information and sliced data using internal mirror-registers for the sliced data, which updated at the same time the header is accessed for reading via the i 2 c bus. i.e. the i 2 c readback header must be always accessed before getting the latest data. in case the sliced data has been read already or is being updated at the time the header is accessed for reading, this will be signalled in the header bits 7 and 5 for each field separately. additionally to the read access to the header the data coming from vbi data slicer is copied into one of the mirror registers only, if the following additional conditions are satisfied: the data type as set in the lcr register must equal to the one of the sampled data. the data must be indicated as valid data. the maximum number of data bytes per line (cc, wss625, gemstar1x:2, cgms:3, gemstar2x: 4) is not exceeded bit header description 7 data of odd ?eld (?eld_id = 0) is incomplete, i.e. not updated since last read, if set. 6 one or more data bytes of odd ?eld (?eld_id = 0) are erroneous (data valid signal became inactive), if set. 5 data of even ?eld (?eld_id = 1) is incomplete. i.e. not updated since last read, if set. 4 one or more data bytes of even ?eld (?eld_id = 1) are erroneous (data valid signal became inactive), if set. 3:1 ?eld_count (counts up, ?eld identi?er represents the lsb)
preliminary nda required con?dential - nda required page 68 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 if there is less data in a line than expected for the appropriate data type, this is marked as an error inside the header. if there is more data in a line, this does not lead to an error, and the additional data bytes are neglected. 8.4.3 s liced vbi d ata o utput at the i-p ort the following sections are describing the sliced vbi payload data output at the i-port. chapter 8.5 describes the output modes for vbi data at the i-port. 8.4.3.1 euro wst, us wst and nabts data euro wst, us wst and nabts data are stored in transmission order; first received bit becomes lsb of byte in payload. 8.4.3.2 wss 625 data each payload byte contains are a group of 6 bits (lsb aligned) representing a single symbol (a wss625 bit) bi-phase coded and then oversampled at 3 times the baud rate. to decode the individual bits, it is usual to take a majority decision on each group of 3 bits (majority of 0s or 1s), then compare the first and second three-bit groups to do bi-phase decoding. 8.4.3.3 wss 525 data the received data contains 20 bits including 6 bits of crc code; all 20 bits are packed into 3 bytes (lsb aligned in byte 3) and written to the packet with the first received bit becoming lsb of the first payload byte. crc checking is performed on the received data (indicated in in the msb of byte 3; set to 0 in case of no errors). unused bytes are set to zero. 8.4.3.4 vps data each pair of two consecutive bits in a payload data byte is a single symbol, biphase coded. 01 represents a 1 symbol,10 represents a 0 symbol. 00 and 11 are biphase errors. the data can be decoded in minimum processor time by using a look-up table (256 bytes) using the received data as index, which gives the correct decoded biphase data in the ls 4 bits of each byte and 4 corresponding error flags; e.g.: a stored byte with hex value 0x1b (binary 00.01.10.11) would be decoded as 1001.0100 (i.e.: the middle two pairs 01 and 10 decode correctly to 1 and 0, but the outer two pairs 00 and 11 are errors). 8.4.3.5 closed caption closed caption is stored in transmission order - first received bit becomes lsb of the first payload byte. 8.4.3.6 moji data the moji data line contains 272 bits, made up of a 14-bit prefix, 22 information data bytes (176 bits) and an 82-bit parity check. the captured bits are constructed into bytes, lsb first, in transmission order, but the first payload byte of the packet contains only 6 bits of trans-mitted data in bits 2 -7. bit 2 corresponds to the first transmitted bit; bits 1 and 0 are filled with zeros. this is done in order to align the information data bytes to byte boundaries in the constructed data packet. it also means that the last data byte in the packet contains only 2 transmitted bits (in positions 0 - 1) - the remaining 6 bits are undefined and should be ignored.
preliminary nda required con?dential - nda required page 69 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.4.3.7 vitc data the vitc data line in both 625- and 525-line video formats contains 90 bits, which can be divided into nine 10-bit groups. the first two bits of each group are defined as synchronising bits, and consist of a fixed 1 followed by a fixed 0 . these synchronising bits are excluded from the data packet constructed by the vbi slicer, leaving exactly nine 8-bit bytes of useful data. the payload bytes are presented in transmission order, with the lsb of each corresponding to the first transmit-ted bit. note that this behaviour is different from the vbi data slicer of the predecessors of the SAA7115 that supported the vitc data types. 8.4.3.8 open data types the open data types are provided primarily to allow capture of low bitrate data types that are not specifically supported by the data capture unit, by oversampling the transmitted data and leaving software to extract the individual bytes. acquisition starts when a match is found for the programmable framing code; bytes are then captured, lsb first, in transmission order at the specified bit-rate. the search window for the framing code is open between approximately 8 and 16ms into the line, referenced to the falling edge of the h-sync pulse. the number of bytes captured in the open data types depends on when in this period the framing code match is found: the maximum numbers of bytes to be received are 38 data bytes for open1 and 43 bytes for open2.they are the maximum assuming earliest possible detection of the framing code. if the framing code is detected any later, fewer bytes may be captured; also, data capture may extend into the region of the following line, in which case the last few data bytes in the packet will be meaningless. it is left up to the software to process the appropriate amount of data from the packet, as defined by the application for which the open data type is being used.
preliminary nda required con?dential - nda required page 70 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.5 image port output interface (subaddresses 84h to 87h) the output interface consists of a fifo for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the i-port and a decoding and multiplexing unit, which generates the 8 or 16-bit wide output data stream and the accompanied reference and supporting information. the clock for the output interface can be derived from an internal clock (decoder or x-port), from the second internal pll set (pll2 and cgc2) or an externally provided clock which is appropriate for e.g. vga and frame buffer. the clock can be up to 33 mhz. the scaler provides the following video related timing reference events (signals), which are available on pins as defined by subaddresses 84h and 85h: output field id start and end of vertical active video range start and end of active video line data qualifier or gated clock actually activated programming page (if conlh is used) threshold controlled fifo filling flags (empty, full, filled) sliced data marker. the data stream at the scaler output is accompanied by a data valid flag (or data qualifier) or is transported using a gated clock. the discontinuous output data after the scaling process can be output as they occur or the data may be packed to continuous output lines by means of a trigger mechanism, which is controlled by a separate pulse generator (see addresses f5h to fbh). clock cycles with invalid data on the i-port data bus (including the hpd pins in 16-bit output mode) are handled in two different ways (controlled by ins80 86h[7]). as before, invalid cycles may be marked with 00h, but additionally a blanking value insertion (80h and 10h) as required by itu656 is now implemented. the output interface also arbitrates the transfer between scaled video data and sliced text data over the i-port output. the bits sldom (5dh) and vitx (86h) are used to control the arbitration. as a further operation the serialization of the internal 32-bit dwords to 8-bit or optional 16-bit output, as well as the insertion of the extended itu 656 codes (sav/eav for video data, anc or sav/eav codes for sliced text data) are done here. for handshake with the vga controller, or other memory or bus interface circuitry, programmable fifo flags are provided (see section 8.5.2).
preliminary nda required con?dential - nda required page 71 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.5.1 s caler output formatter ( subaddresses 93h and c3h) the output formatter organizes the packing into the output fifo. the following formats are available: y-c b -c r 4:2:2, y- c b -c r 4:1:1, y-c b -c r 4:2:0, y-c b -c r 4:1:0, y only (e.g. for raw samples). the formatting is controlled by fsi[2:0] 93h[2:0], foi[1:0] 93h[4:3] and fysk[93h[5]]. the data formats are defined on dwords, or multiples, and are similar to the video formats as recommended for pci multimedia applications, but planar formats are not supported. fsi[2:0] defines the horizontal packing of the data, foi[1:0] defines how many y only lines are expected, before a y/c line will be formatted. if fysk is set to logic 0 preceding y only lines will be skipped, and the output will always start with a y/c line. additionally the output formatter limits the amplitude range of the video data (controlled by illv[85h[5]]); see table 23. table 21 byte stream for different output formats table 22 explanation to table 21 table 23 limiting range on i-port 8.5.2 v ideo fifo ( subaddress 86h) the video fifo at the scaler output contains 32 dwords. that corresponds to 64 pixels in 16-bit y-c b -c r 4:2:2 format. but as the entire scaler can act as a pipeline buffer, the actual available buffer capacity for the image port is much higher, and can exceed beyond a video line. the video fifo provides 4 internal flags, reporting to what extent the fifo is actually filled. these are: the fifo almost empty (fae) flag the fifo combined flag (fcf) or fifo filled, which is set at almost full level and reset, with hysteresis, only after the level crosses below the almost empty mark the fifo almost full (faf) flag the fifo overflow (fovl) flag. output format byte sequence for 8-bit output modes y-cb-cr 4 : 2 : 2 cb0 y0 cr0 y1 cb2 y2 cr2 y3 cb4 y4 cr4 y5 cb6 y6 y-cb-cr 4 : 1 : 1 cb0 y0 cr0 y1 cb4 y2 cr4 y3 y4 y5 y6 y7 cb8 y8 y only y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 name explanation cbn cb (b - y) colour difference component, pixel number n = 0, 2, 4 to 718 yn y (luminance) component, pixel number n = 0, 1, 2, 3 to 719 crn cr (r - y) colour difference component, pixel number n = 0, 2, 4 to 718 limit step illv[85h[5]] valid range suppressed codes (hexadecimal value) decimal value hexadecimal value lower range upper range 0 1 to 254 01 to fe 00 ff 1 8 to 247 08 to f7 00 to 07 f8 to ff
preliminary nda required con?dential - nda required page 72 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 the trigger levels for fae and faf are programmable by ffl[1:0] 86h[3:2] (16, 24, 28, full) and fel[1:0] 86h[1:0] (16, 8, 4, empty). the state of this flag can be seen on the pins igp0 or igp1. the pin mapping is defined by subaddresses 84h and 85h (see section 9.5). 8.5.3 t ext fifo the data of the internal vbi-data slicer is collected in the text fifo before the transmission over the i-port is requested (normally before the video window starts). it is partitioned into two fifo sections. a complete line is filled into the fifo before a data transfer is requested. so normally, one line of text data is ready for transfer, while the next text line is collected. thus sliced text data is delivered as a block of qualified data, without any qualification gaps in the byte stream of the i-port. the decoded vbi-data is collected in the dedicated vbi-data fifo. after capture of a line is completed, the fifo can be streamed through the image port, preceded by a header, telling line number and standard. the vbi-data period can be signalled via the sliced data flag on pin igp0 or igp1. the decoded vbi-data is lead by the itu ancillary data header (sldom[4:0] 5dh[5:0] at value > 0h and <8h) or by sav/eav codes (sldom[4:0] 5dh[5:0] at value > 0h and bit d3 = 1 ). similar to the global data qualifier on pin idq, the sliced data flag frames the transfer of sliced vbi data from the first to the last byte and can be taken to distinguish video from sliced vbi data. the decoded vbi-data are presented in two different data formats, controlled by bit d0 of sldom[4:0]. sldom[0] = 1: values 00h and ffh will be recoded to even parity values 03h and fch sldom[0] = 0: values 00h and ffh may occur in the data stream as detected. 8.5.4 v ideo / text arbitration and d ata packing ( subaddress 86h) sliced text data and scaled video data are transferred over the same bus, the i-port. the mixed transfer is controlled by an arbitration circuit and the sldom programming. if the video data are output for the whole field (also during vertical blanking) and the video fifo does not need to buffer any output pixel, the text data is inserted after the end of a scaled video line, normally during the horizontal blanking interval of the video. 8.5.4.1 vbi insertion in sav/eav mode (bit sldom[3] = 1) vbi insertion in sav/eav mode (bit sldom[3] = 1): especially for external devices, which do not recognize the anc framing of the sliced vbi data and which need to use the sav/eav framing, there are now different levels of vbi/video data insertion implemented. this functionality is controlled by sldom [5dh]. levels of sliced data insertion: 1. sldom[4] = 0: video and sliced data, according sldom[1], in parallel, vbi data after eav sequence of a video line 2. sldom[4] = 1: sliced data, according sldom[1], video output is skipped for these lines note: 1.the insertion after eav and the skipping is only done, if the scaler region overlaps with the lcr defined vbi region.
preliminary nda required con?dential - nda required page 73 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.5.4.2 data packing (bit impak (86h) and programming of the pulse generator via addr. f5h to fbh) to make use of the synthesized line locked pll2 clock and to enable the use of the scaler for a wider application range, it is now possible to retain the output data of the scaler, until a scaled line can be output as a continuous data package. this is done via internal trigger pulses, one for each type of scaler output data (video from page a or b or sliced vbi data). the parameters pghaps (video page a), pghbps (video page b) and pghcps (sliced vbi data) are defining the delay related to the rising edge of the decoders href or of the synthesized href (generated by the internal pulse generator, see addr. f5h and f6h). the delay is counted in clock cycles and as a rough estimate for the internal buffering level you can take the following equation for the video data streaming. with num_buf_pix = number of buffered pixel, num_buf_lifo = number of pixel buffered in the internal line fifo num_buf_fifo = number of pixel buffered in the output fifo h_blanking = number of clock cycles during horizontal blanking = 288 (pal), 276 (ntsc) sc_run_in = number of clock cycles for scaler running in = about 72 clock cycles for unscaled video num_buf_pix is about ~= (pghaps - h_blanking - sc_run_in) / 2 = num_buf_lifo + num_buf_fifo where num_buf_lifo = 0 for num_buf_pix =< 64 and the maximum value of num_buf_lifo = 768dec num_buf_fifo = 64 for num_buf_pix > 64 for unscaled video a level around 1/2 of the buffer capacity (num_buf_lifo + num_buf_fifo = 832dec) is recommended. this leads to a pghaps value of about ~= 2 x 416 + h_blanking + sc_run_in = 1192 (pal case) for the unscaled case. to be able to align the eav sequences for different scales and regions, pghbps of page b is a separate parameter. the number of bytes per line and region defines, whether pghbps is to be programmed differently to pghaps. if all data types are to be mixed and a fixed sav/eav pattern is needed, the vbi slicer has to become the timing master for the data packing. to avoid timing shifts in the eav pattern, the latest point of text line completion defines the earliest packing timing. this is about 48 clocks before rising edge of the decoders href. the slicer data need to be shifted to a position later than this point. the latest point in time is defined by the internal video skipping procedure (sldom[4] =1). therefore the end of a video line (eav) need to have a distance of (number of pixels per line) of clock cycles from the mentioned point of text line completion. considering the pll behaviour and for correct video skipping, the recommendation for this situation and eav alignment for 720 pixel per line and pal (=1728) is: 1728 - (48+56) - 720 - 1448 = -544 = 1184 >= pghcps >= 1728 - (48-20) = 1700 pghaps = pghcps - num_bytes_per_video_line + num_bytes_per_vbi_package = e.g. 1700 - 1448 + 56 = 308dec for other clock rates than 27 mhz, the mentioned values need to be scaled according to the clock relations, e.g. 24.545454 mhz would give 1560 - 94 - 640 - 1288 = -462 = 1098 >= pghcps >= 1560 - 25 = 1535 pghaps = e.g. 500 - 1288 + 51 = -737 = 823dec 8.5.5 d ata stream coding and reference signal generation ( subaddresses 84h, 85h and 93h) as h and v reference signals are logic 1, active gate signals are generated, which frame the transfer of the valid output data. as an alternative to the gates, h and v trigger pulses are generated on the rising edges of the gates. due to the dynamic fifo behaviour of the complete scaler path, the output signal timing has no fixed timing relationship to the real-time input video stream. so fixed propagation delays, in terms of clock cycles, related to the analog input cannot be defined. the data stream is accompanied by a data qualifier. itu 656 like codes need to be activated by means of the bit icode set to 1. the behaviour during non qualified clock cycles is defined by the bit ins80 [93h[6]]. with ins80 = 0 the interface behaves like saa7118/7114 and invalid data cycles are marked with code 00h.
preliminary nda required con?dential - nda required page 74 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 for ins80 =1 the behaviour changes and inside the scalers output line (scaler h-gate on igph = 1), the data are hold during idq =0. outside the scalers output, in the remaining horizontal blanking interval, blanking values are inserted. as a further option, it is possible to provide the scaler with an external gating signal on pin itrdy. thereby making it possible to hold the data output for a certain time and to get valid output data in bursts of a guaranteed length. the sketched reference signals and events can be mapped to the i-port output pins idq, igph, igpv, igp0 and igp1. for flexible use the polarities of all the outputs can be modified. the default polarity for the qualifier and reference signals is logic 1 (active). table 24 shows the relevant and supported sav and eav coding, the figures 34, 33, 35, 36 show some basic pulse diagrams. table 24 sav/eav codes on i-port notes 1. the leading byte sequence is: ffh-00h-00h. 2. the msb of the sav/eav code byte is controlled by: a) scaler output data: task a t msb = conlh[90h[7]]; task b t msb = conlh[c0h[7]]. b) vbi-data slicer output data: sldom[2] = 1 t msb = 1; sldom[2] = 0 t msb = 0. event description sav/eav codes on i-port (1) (hex) comment msb (2) of sav/eav byte = 0 msb (2) of sav/eav byte = 1 field id = 0 field id = 1 field id = 0 field id = 1 next pixel is first pixel of any active line 0e 49 80 c7 href = active; vref = active previous pixel was last pixel of any active line, but not the last 13 54 9d da href = inactive; vref = active next pixel is first pixel of any v-blanking line 25 62 ab ec href = active; vref = inactive previous pixel was last pixel of the last active line or of any v-blanking line 38 7f b6 f1 href = inactive; vref = inactive no valid data, dont capture and dont increment pointer 00 (only for ins80 = 0) idq pin inactive
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 75 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required fig.31 sliced data formats on the i-port in 8-bit mode timing ref. code timing ref. code invalid data ... internal header sliced data ff 00 00 sav sdid dc d 2_2 d 2_1 idi1 idi2 d dc_2 d dc_1 ff 00 00 eav 00 00 00 00 ... ... 00 ff ff did 00 00 00 eav ... or end of raw vbi line invalid data ... - data output is ?lled upto the dc count d 2_3 and filling data dword - boundary anc header internal header sdid dc d 2_2 d 2_1 idi1 idi2 ... d dc_2 d dc_1 sliced data ff 00 - anc header active for sldom[3] = 0 bc cs d 1_2 d 1_1 bc cs ... and filling data d 1_4 d 1_3 d dc_3 d dc_4 d 1_2 d 1_1 d 1_4 d 1_3 d dc_3 d dc_4
preliminary nda required con?dential - nda required page 76 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 25 explanation to fig.31 notes 1. inverted ep (bit 7); for ep see note 2. 2. even parity (bit 6) of bits 5 to 0. 3. odd parity (bit 7) of bits 6 to 0. name explanation sav start of active data; see table 26 sdid sliced data identi?cation: nep (1) , ep (2) , sdid5 to sdid0, freely programmable via i2c-bus subaddress 5eh, d5 to d0, e. g. to be used as source identi?er dc dword count: nep (1) , ep (2) , dc5 to dc0. dc describes the number of succeeding 32-bit words: for sav/eav mode dc is fixed to 12 dwords (byte value 8ch) for anc mode the data count dc can be taken from table 27. the count starts with the sdid byte and ends with bc it should be noted that the number of valid bytes inside the stream can be seen in the bc byte. idi1 internal data identi?cation 1: op (3) , fid (?eld 1 = 0, ?eld 2 = 1), linenumber8 to linenumber3 = dword 1 byte 1; see table 26 idi2 internal data identi?cation 2: op (3) , linenumber2 to linenumber0, datatype3 to datatype0 = dword 1 byte 2; see table 26 dn_m dword number n, byte number m ddc_4 last dword byte 4, note: for sav/eav framing dc is ?xed to 0bh, missing data bytes are ?lled up; the ?ll value is a0h cs the check sum byte, the check sum is accumulated from the sav (respectively did) byte to the ddc_4 byte bc number of valid sliced bytes counted from the d1_3 byte eav end of active data; see table 26
preliminary nda required con?dential - nda required page 77 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 26 bytes stream of the data slicer notes 1. nep = inverted ep (see note 2). 2. ep = even parity of bits 5 to 0. 3. fid = 0: field 1; fid = 1: field 2. 4. i1 = 0 and i0 = 0: before line 1; i1 = 0 and i0 = 1: lines 1 to 23; i1 = 1 and i0 = 0: after line 23; i1 = 1 and i0 = 1: line 24 to end of field. 5. subaddress 5dh at 3eh and 3fh are used for itu 656 like sav/eav header generation; recommended value. 6. v = 0: active video; v = 1: blanking. 7. h = 0: start of line; h = 1: end of line. 8. dc = data count in dwords according to the data type. 9. op = odd parity of bits 6 to 0. 10. ln = line number. 11. dt = data type according to table. nick name comment d7 d6 d5 d4 d3 d2 d1 d0 did, sav, eav subaddress 5dh sldom[3:2] = 00 nep ep 0 d4[5dh] d3[5dh] d2[5dh] d1[5dh] d0[5dh] subaddress 5dh sldom[3:2] = 01 nep (1) ep (2) 010fid (3) i1 (4) i0 (4) subaddress 5dh sldom[3:2] = 10 0 fid (3) v (6) h (7) p3 p2 p1 p0 subaddress 5dh sldom[3:2] = 11 1 fid (3) v (6) h (7) p3 p2 p1 p0 sdid programmable via subaddress 5eh nep ep d5[5eh] d4[5eh] d3[5eh] d2[5eh] d1[5eh] d0[5eh] dc (8) nep ep (2) dc5 dc4 dc3 dc2 dc1 dc0 idi1 op (9) fid (3) ln8 (10) ln7 (10) ln6 (10) ln5 (10) ln4 (10) ln3 (10) idi2 op ln2 (10) ln1 (10) ln0 (10) dt3 (11) dt2 (11) dt1 (11) dt0 (11) cs check sum byte cs6 cs6 cs5 cs4 cs3 cs2 cs1 cs0 bc valid byte count op 0 cnt5 cnt4 cnt3 cnt2 cnt1 cnt0
preliminary nda required con?dential - nda required page 78 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 27 data count (dc) in anc mode for the various vbi standards notes 1. nop = no data output data type 50hz / 625 lines 60hz / 525 lines no. binary data count (dc) in 32 bit dw data count (dc) in 32 bit dw 0 0000 nop nop 1 0001 12 10 2 0010 12 10 3 0011 nop 11 4 0100 2 2 5 0101 5 3 6 0110 5 5 7 0111 8 3 8 1000 nop 3 9 1001 2 2 10 1010 12 12 11 1011 12 12 12 1100 nop nop 13 1101 nop nop 14 1110 nop nop 15 1111 nop nop
preliminary nda required con?dential - nda required page 79 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.6 scaler backend clock generation (subaddresses 30h to 3fh) the SAA7115 incorporates with its audio clock pll (apll), its second digital pll (pll2) and its second analog pll (cgc2) the generation of multiple different clocks for internal and external usage. the following types of clocks can be generated: a backend clock to drive the scaler backend including image port data output (refer to chapter 8.6.1): this is an internal clock which is used for the output of data at the image port (i-port). it can be defined as a square pixel clock for pal and ntsc (29,5 mhz and 24,5454 mhz respectively). a frame locked audio master clock (output at device pin 37, amclk; refer to chapter 8.7): this clock, which is locked to the frame frequency, ensures that there is always the same predefined number of audio samples associated with a frame. this ensures e.g. synchronous recording of audio and video (e.g. capture to hard disk, or non-linear editing). (digital) audio pll second pll (pll2) 6 6 cgc2 dac 6 dto msb only aslrclk asclk alrclk amxclk amclk v-pulse line based reference frame reference fig.32 square pixel clock and audio clock generation h-pulse (pin 37) (pin 41) (pin 39) (pin 40) 1/4 1/3 backend 1/4 clock ucgc cgcdiv
preliminary nda required con?dential - nda required page 80 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.6.1 s quare p ixel c lock g eneration the SAA7115 is capable to output video data especially in square pixel formats. i.e.: pal video line (625 lines per frame) is output with 768/176 continuous active/inactive video pixel at 29.5 mhz clock frequency ntsc video line(525 lines per frame) is output with 640/140 continuous active/inactive video pixel at 24.54 mhz clock frequency. to generate the clock which allows a continuous data stream at the image port the SAA7115 has implemented the second analog pll (cgc2) which is stimulated by the line locked second digital pll (pll2, alias square pixel pll). the cgc2 output clock drives the scaler backend and the pulse generator to deliver video data with square pixel format at the i-port. to avoid scaler fifo overflows/underruns the pixel clock must be phase aligned to the video input signal. hence the reference of the second digital pll (pll2) is a horizontal reference signal obtained from the combfilter decoder or the x-port input xrh (controlled by sphsel, register address f1 h [d1]). only the square pixel clock frequencies of 29.5 mhz and 24.5454 mhz are targeted for driving the scaler backend with pll2 / cgc2. 8.6.1.1 the second pll (pll2) the second pll (pll2) consists of a discrete time oscillator (dto), a phase detector which computes the phase error once per video line while taking into account the current dto phase and a pi -loop filter with programmable p/i coefficients. if the phase error become less then a programmed locking threshold value spthrm [3:0] (register address ff h [3:0]) for a period of time defined number of lines programmed in spthrl [3:0] register (register address ff h [7:4]), the pll2 indicates the status locked. if the pll is locked, a status register splock (register address f1h [0]) is set. the pll2 is controlled by the following settings: number of target clock cycles per line divided by 4 (splpl, register addresses f1 h [d0], f0 h [d7:d0] nominal dto increment (spninc, register addresses f3 h [d7:d0], f2 h [d7:d0]): the nominal increment is basic clock frequency setting for pll2 and hence for cgc2 clock output (cgc2frequency, in scaler backend clock generation mode). if pll2 is opened it is the only parameter which defines the defines the clock frequency. it depends on the crystal frequency (32.11 mhz or 24.576 mhz) and is calculated as: pll2 operation mode (spmod, register address f1 h [d3:d2]): C pll-closed (normal operation mode, spmod = 01 bin): this is the normal operation mode of the second pll (pll2): the nominal increment plus the content of loop filter define the output (cgc2) frequency. C synthesize clock mode (spmod = 00 bin): the pll2 is opened and hence the generated clock frequency at cgc2 output depends only on the nominal increment defined by the register spninc. the contribution of the loop filter is disabled. the i and p proportion of the loop filter is set to zero. C pll-hold (spmod = 10 bin): the cgc2 output keeps the same clock frequency which was generated when entering this mode. in this mode content of the loop filter of pll2 will be frozen. C pll-re-sync (spmod = 11 bin) the phase detector of pll2 is continuously re-synchronized to the selected horizontal reference signal controlled by sphsel. the remaining phase error is fed into the loop filter. loop filter mode (p/i parameter selection; sppi, register address f1 h [d7:d4]): as long as the pll2 is in un-locked state the loop filter operates at a fast time constant to enable fast locking to the spinc integer cgc2frequency 4 xtalfrequency ------------------------------------------------------ ? ?? 2 16 ? ?? =
preliminary nda required con?dential - nda required page 81 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 input signal. as soon as the status is locked the pi-filter is controlled by the sppi setting. four different modes can be selected controlled via sppi: C mode 0 h (default); adaptive mode: the proportional part is controlled dynamically by the magnitude of the phase error. C mode 1 h; fast mode both p and i parameters of the loop filter remain on the unlocked values, even if pll2 has locked. C mode e h; medium mode: the proportional part (p) of the loop filter is set to a medium value and the integral part (i) is set to minimum. C mode f h; slow mode: both the proportional part and the integral part are set to minimum value.
preliminary nda required con?dential - nda required page 82 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.7 audio clock generation (subaddresses 30h to 3fh) the SAA7115 incorporates with its audio clock pll (apll), its second analog pll (cgc2) the generation of multiple different audio clocks for external usage. there are two basic modes for generating an audio clock (refer to figure 32): generating a frame locked audio master clock without using the second analog pll (cgc2) (refer to chapter 8.7.1): this frame locked audio clock is directly obtained from the digital audio pll and output at the device pin amclk (pin 37). hence this signal carries the correct number of clock cycles per frame but still has a high frequency jitter. this clock can be fed to an external pll and than returned to the amxclk pin (pin 41) to generate an serial bitclock - output at the asclk pin (pin 39) - and a word select signal - output at the alrclk pin (pin 40). using this audio clock generation method audio clock frequencies it is not possible to generate frequencies of 384*fs and 512*fs (fs = audio sampling frequency) generating a low jitter frame locked audio master clock supported by the second analog pll (cgc2) (refer to chapter 8.7.2): in this mode the digital audio pll output signal feeds the internal second analog pll (cgc2) to remove high frequency jitter from the audio clock signal. the resulting clock is output at the device pin amclk (pin 37). this is already the audio clock for some high frequency audio clocks. all other audio clocks must be generated by feeding back the amclk output signal into the amxclk input pin. the audio clock frequency will be defined by the programming value of the sdiv[5:0] register (subaddress 38hex) and output at the asclk output pin (pin 39). both modes ensure that there is always the same predefined number of audio samples associated with a frame, because the audio clock is locked to the frame frequency. 8.7.1 a udio clock generation without analog pll (cgc2) enhancement 8.7.1.1 master audio clock the audio clock is synthesized from the same crystal frequency as the line-locked video clock is generated. the master audio clock is defined by the parameters: audio master clocks per field, acpf[17:0] 32h[1:0] 31h[7:0] 30h[7:0] according to the equation: audio master clocks nominal increment, acni[21:0] 36h[5:0] 35h[7:0] 34h[7:0] according to the equation: see table 28 for examples. remark : for standard applications the synthesized audio clock amclk can be used directly as master clock and as input clock for port amxclk (short cut) to generate asclk and alrclk. for high-end applications it is recommended to either use the second cgc for audio clock generation by setting ucgc = 1 (see subaddress 3ah, bit 7) or use an external analog pll circuit to enhance the performance of the generated audio clock. acpf[17:0] round audio master clock frequency field frequency ----------------------------------------------------------------------------- - ? ?? = acni[21:0] round audio master clock frequency crystal frequency ----------------------------------------------------------------------------- - 2 23 ? ?? =
preliminary nda required con?dential - nda required page 83 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 28 programming examples for audio master clock generation (no cgc2 support) 8.7.1.2 signals asclk and alrclk two binary divided signals asclk and alrclk are provided for slower serial digital audio signal transmission and for channel-select. the frequencies of these signals are defined by the following parameters: sdiv[5:0] 38h[5:0] according to the equation: t lrdiv[5:0] 39h[5:0] according to the equation: t see table 29 for examples. xtalo (mhz) field (hz) acpf acni decimal hex decimal hex amclk = 256 48 khz (12.288 mhz) 32.11 50 245760 3c000 3210190 30fbce 59.94 205005 320cd 3210190 30fbce 24.576 50 ---- 59.94 ---- amclk = 256 44.1 khz (11.2896 mhz) 32.11 50 225792 37200 2949362 2d00f2 59.94 188348 2dfbc 2949362 2d00f2 24.576 50 225792 37200 3853517 3acccd 59.94 188348 2dfbc 3853 517 3acccd amclk = 256 32 khz (8.192 mhz) 32.11 50 163840 28000 2140127 20a7df 59.94 136670 215de 2140127 20a7df 24.576 50 163840 28000 2796203 2aaaab 59.94 136670 215de 2796203 2aaaab f asclk f amxclk sdiv 1 + () 2 ------------------------------------- - = sdiv[5:0] f amxclk 2f asclk ------------------- - 1 C = f alrclk f asclk lrdiv 2 -------------------------- - = lrdiv[5:0] f asclk 2f alrclk ---------------------- - =
preliminary nda required con?dential - nda required page 84 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 29 programming examples for asclk/alrclk clock generation 8.7.2 a udio clock generation with analog pll (cgc2) support when generating the audio clock using the second analog pll (cgc2) the cgc2 is driven by the digital audio clock pll. the output of cgc2 again is output at the audio master clock output pin amclk (pin 37) controlled by the ucgc (address 3a h [7]) programming register. for audio clock frequencies of 512 * fs, with fs = 48.0 khz or 44.1 khz this is already the low jitter audio clock. all other low jitter audio clocks are output at the asclk pin (pin 39) using the internal divider controlled by sdiv (address 38 h [5:0]) programming register (refer to table 30 and 31). therefore the audio master clock amclk must be returned into the device via the amxclk pin (pin 41). the audio master clock again is synthesized from the same crystal frequency as the line-locked video clock and is defined as: audio master clocks per field, acpf[17:0] 32h[1:0] 31h[7:0] 30h[7:0] according to the equation: audio master clocks nominal increment, acni[21:0] 36h[5:0] 35h[7:0] 34h[7:0] according to the equation: note that in this case the audio master clock is not identical to the clock output by the digital audio clock pll any more. the second analog pll (cgc2) operates at a centre frequency of 36 mhz if cgcdiv (register address 3a h [6]) is set to 1 and 27 mhz if cgcdiv is set to 0. cgc2 can operate in a range of -18% and +15.8% around these centre frequencies. amxclk (mhz) asclk (khz) sdiv alrclk (khz) lrdiv decimal hex decimal hex 12.288 1536 3 03 48 16 10 768 7 07 8 08 11.2896 1411.2 3 03 44.1 16 10 2822.4 1 01 32 10 8.192 1024 3 03 32 16 10 2048 1 01 32 10 acpf[17:0] round audio master clock frequency field frequency ----------------------------------------------------------------------------- - ? ?? 4 cgcdiv C () 16 --------------------------------------- ? ?? ? ?? = acni[21:0] round audio master clock frequency crystal frequency ----------------------------------------------------------------------------- - 2 23 ? ?? 4 cgcdiv C () 16 --------------------------------------- ? ?? ? ?? =
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 85 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required table 30 programming examples for frame locked audio clock generation supported by cgc2, fxtal = 24.576 mhz, 625 /525 line systems n * fs cgcdiv [bin] amclk freq. [mhz] acni acpf sdiv amxclk / asclk ratio audio clock [dec] [hex] 625 / 525 [dec] [hex] [dec] [hex] [mhz] output pin (amclk / asclk) fs = 48 khz 512 0 24.576 2097152 200000 122880 / 102502 1e000 / 19066 na. na. na. 24.576 amclk 384 1 36.864 2359296 240000 138240 / 115315 21c00 / 1c273 0 00 2 18.432 asclk 256 0 24.576 2097152 200000 122880 / 102502 1e000 / 19066 0 00 2 12.288 asclk 192 1 36.864 2359296 240000 138240 / 115315 21c00 / 1c273 1 01 4 9.216 asclk 128 1 36.864 2359296 240000 138240 / 115315 21c00 / 1c273 2 02 6 6.144 asclk 96 1 36.864 2359296 240000 138240 / 115315 21c00 / 1c273 3 03 8 4.608 asclk 64 1 36.864 2359296 240000 138240 / 115315 21c00 / 1c273 5 05 12 3.072 asclk 48 1 36.864 2359296 240000 138240 / 115315 21c00 / 1c273 7 07 16 2.304 asclk 32 1 36.864 2359296 240000 138240 / 115315 21c00 / 1c273 11 0b 24 1.536 asclk fs = 44.1 khz 512 0 22.5792 1926758 1d6666 112896 / 94174 1b900 / 16fde na. na. na. 22.5792 amclk 384 1 33.8688 2167603 211333 127008 / 105946 1f020 / 19dda 0 00 2 16.9344 asclk 256 0 22.5792 1926758 1d6666 112896 / 94174 1b900 / 16fde 0 00 2 11.2896 asclk 192 1 33.8688 2167603 211333 127008 / 105946 1f020 / 19dda 1 01 4 8.4672 asclk 128 1 33.8688 2167603 211333 127008 / 105946 1f020 / 19dda 2 02 6 5.6448 asclk
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 86 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required 96 1 33.8688 2167603 211333 127008 / 105946 1f020 / 19dda 3 03 8 4.2336 asclk 64 1 33.8688 2167603 211333 127008 / 105946 1f020 / 19dda 6 06 12 2.8224 asclk 48 1 33.8688 2167603 211333 127008 / 105946 1f020 / 19dda 7 07 14 2.1168 asclk 32 1 33.8688 2167603 211333 127008 / 105946 1f020 / 19dda 11 0b 24 1.4112 asclk fs = 32 khz 512 1 32.768 2097152 200000 122880 / 102502 1e000 / 19066 0 00 2 16.384 asclk 384 0 24.576 2097152 200000 122880 / 102502 1e000 / 19066 0 00 2 12.288 asclk 256 1 32.768 2097152 200000 122880 / 102502 1e000 / 19066 1 01 4 8.192 asclk 192 1 36.864 2359296 240000 138240 / 115315 21c00 / 1c273 2 02 6 6.144 asclk 128 0 24.576 2097152 200000 122880 / 102502 1e000 / 19066 2 02 6 4.096 asclk 96 1 36.864 2359296 240000 138240 / 115315 21c00 / 1c273 5 05 12 3.072 asclk 64 1 36.864 2359296 240000 138240 / 115315 21c00 / 1c273 8 08 18 2.048 asclk 48 1 36.864 2359296 240000 138240 / 115315 21c00 / 1c273 11 0b 24 1.536 asclk 32 1 36.864 2359296 240000 138240 / 115315 21c00 / 1c273 17 11 36 1.024 asclk n * fs cgcdiv [bin] amclk freq. [mhz] acni acpf sdiv amxclk / asclk ratio audio clock [dec] [hex] 625 / 525 [dec] [hex] [dec] [hex] [mhz] output pin (amclk / asclk)
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 87 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required table 31 programming examples for frame locked audio clock generation supported by cgc2, fxtal = 32.11mhz, 625 /525 line systems n * fs cgcdiv [bin] amclk freq. [mhz] acni acpf sdiv amxclk / asclk ratio audio clock [dec] [hex] 625 / 525 [dec] [hex] [dec] [hex] [mhz] output pin (amclk / asclk) fs = 48 khz 512 0 24.576 1605095 187de7 122880 / 102502 1e000 / 19066 na. na. na. 24.576 amclk 384 1 36.864 1805732 1b8da4 138240 / 115315 21c00 / 1c273 0 00 2 18.432 asclk 256 0 24.576 1605095 187de7 122880 / 102502 1e000 / 19066 0 00 2 12.288 asclk 192 1 36.864 1805732 1b8da4 138240 / 115315 21c00 / 1c273 1 01 4 9.216 asclk 128 1 36.864 1805732 1b8da4 138240 / 115315 21c00 / 1c273 2 02 6 6.144 asclk 96 1 36.864 1805732 1b8da4 138240 / 115315 21c00 / 1c273 3 03 8 4.608 asclk 64 1 36.864 1805732 1b8da4 138240 / 115315 21c00 / 1c273 5 05 12 3.072 asclk 48 1 36.864 1805732 1b8da4 138240 / 115315 21c00 / 1c273 7 07 16 2.304 asclk 32 1 36.864 1805732 1b8da4 138240 / 115315 21c00 / 1c273 11 0b 24 1.536 asclk fs = 44.1 khz 512 0 22.5792 1474681 168079 112896 / 94174 1b900 / 16fde na. na. na. 22.5792 amclk 384 1 33.8688 1659016 195088 127008 / 105946 1f020 / 19dda 0 00 2 16.9344 asclk 256 0 22.5792 1474681 168079 112896 / 94174 1b900 / 16fde 0 00 2 11.2896 asclk 192 1 33.8688 1659016 195088 127008 / 105946 1f020 / 19dda 1 01 4 8.4672 asclk 128 1 33.8688 1659016 195088 127008 / 105946 1f020 / 19dda 2 02 6 5.6448 asclk
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 88 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required 96 1 33.8688 1659016 195088 127008 / 105946 1f020 / 19dda 3 03 8 4.2336 asclk 64 1 33.8688 1659016 195088 127008 / 105946 1f020 / 19dda 6 06 12 2.8224 asclk 48 1 33.8688 1659016 195088 127008 / 105946 1f020 / 19dda 7 07 14 2.1168 asclk 32 1 33.8688 1659016 195088 127008 / 105946 1f020 / 19dda 11 0b 24 1.4112 asclk fs = 32 khz 512 1 32.768 1605095 187de7 122880 / 102502 1e000 / 19066 0 00 2 16.384 asclk 384 0 24.576 1605095 187de7 122880 / 102502 1e000 / 19066 0 00 2 12.288 asclk 256 1 32.768 1605095 187de7 122880 / 102502 1e000 / 19066 1 01 4 8.192 asclk 192 1 36.864 1805732 1b8da4 138240 / 115315 21c00 / 1c273 2 02 6 6.144 asclk 128 0 24.576 1605095 187de7 122880 / 102502 1e000 / 19066 2 02 6 4.096 asclk 96 1 36.864 1805732 1b8da4 138240 / 115315 21c00 / 1c273 5 05 12 3.072 asclk 64 1 36.864 1805732 1b8da4 138240 / 115315 21c00 / 1c273 8 08 18 2.048 asclk 48 1 36.864 1805732 1b8da4 138240 / 115315 21c00 / 1c273 11 0b 24 1.536 asclk 32 1 36.864 1805732 1b8da4 138240 / 115315 21c00 / 1c273 17 11 36 1.024 asclk n * fs cgcdiv [bin] amclk freq. [mhz] acni acpf sdiv amxclk / asclk ratio audio clock [dec] [hex] 625 / 525 [dec] [hex] [dec] [hex] [mhz] output pin (amclk / asclk)
preliminary nda required con?dential - nda required page 89 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 8.7.3 o ther control signals for audio clock generation further control signals are available to define reference clock edges and vertical references: apll[3ah[3]]; audio pll mode: 0: pll closed 1: pll open amvr[3ah[2]]; audio master clock vertical reference: 0: internal v 1: external v lrph[3ah[1]]; alrclk phase 0: invert asclk, alrclk edges triggered by falling edge of asclk 1: dont invert asclk, alrclk edges triggered by rising edge of asclk scph[3ah[0]]; asclk phase: 0: invert amxclk, asclk edges triggered by falling edge of amxclk 1: dont invert amxclk, asclk edges triggered by rising edge of amxclk.
preliminary nda required con?dential - nda required page 90 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 9 input/output interfaces and ports the SAA7115 has 5 different i/o interfaces: analog video input interface, for analog cvbs and/or y and c input signals audio clock port digital real-time signal port (rt port) digital video expansion port (x-port), for unscaled digital video input and output digital image port (i-port) for scaled video data output and programming digital host port (h-port) for extension of the image port (output mode) or expansion port (input mode) from 8 to 16-bit. 9.1 analog terminals the SAA7115 has 6 analog inputs ai21 to ai24 and ai11 to ai12 for composite video cvbs or s-video y/c signal pairs. additionally, there are two differential reference inputs, which must be connected to ground via a capacitor equivalent to the decoupling capacitors at the 6 inputs. per connected input there are no peripheral components required other than a decoupling capacitor of 47nf directly connected to the analog device inputs pins), an 18 w (connected in series directly to the source) and 56 w (connected between the capacitor and the 18 w resistor to ground) termination resistor. two anti-alias filters are integrated. clamp and gain control for the adcs are also integrated. an analog video output (pin aout) is provided for testing purposes. table 32 analog pin description 9.2 audio clock signals the SAA7115 also synchronizes the audio clock and sampling rate to the video frame rate, via a very slow pll. this ensures that the multimedia capture and compression processes always gather the same predefined number of samples per video frame. there are two basic modes as described in chapter 8.7 . depending on these modes the signals amclk, asclk and alrclk are generated (note: to generate asclk and alrclk the audio master clock amclk must be fed back into the device via the amxclk pin.). generating a frame locked audio master clock without using the second analog pll (cgc2): C amclk: is the audio clock. C asclk: can be used as audio serial clock. C alrclk: audio left/right channel clock. generating a low jitter frame locked audio master clock supported by the second analog pll (cgc2): C amclk: is the audio clock for 512*fs (fs = 48khz or 44.1khz). symbol pin i/o description bit ai11 and ai12 20, 18 i analog video signal inputs, e.g. six cvbs signals or two y/c plus two cvbs pairs signal groups can be connected simultaneously to this device; several combinations are possible; see table 54. mode3 to mode0 (02h[3:0]) ai21, ai22, ai23 and ai24 16, 14, 12, 10 aout 22 o analog video output, for test purposes aosl2 to aosl0 (01h[7], 14h[5:4]) ai1d, ai2d 19, 13 i analog reference pins for differential adc operation; connect to ground via 47 nf -
preliminary nda required con?dential - nda required page 91 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 C asclk: is the audio clock for all other audio clock frequencies. the ratios are programmable; see also chapter 8.7. table 33 audio clock pin description 9.3 clock and real-time synchronization signals for the generation of the line-locked video (pixel) clock llc, and of the frame-locked audio serial bit clock, a crystal accurate frequency reference is required. an oscillator is built-in for fundamental or third harmonic crystals. the supported crystal frequencies are 32.11 mhz and 24.576 mhz (defined during reset by strapping pin alrclk). alternatively pin xtali can be driven from an external single-ended oscillator. the crystal oscillation can be propagated as a clock to other ics in the system via pin xtout. the line-locked clock (llc) is the double pixel clock of nominal 27 mhz. it is locked to the selected video input, generating baseband video pixels according to itu recommendation 601 . in order to support interfacing circuits, a direct pixel clock (llc2) is also provided. the pins for line and field timing reference signals are rtco, rts1 and rts0. various real-time status information can be selected for the rts pins. the signals are always available (output) and reflect the synchronization operation of the decoder part in the SAA7115. the function of the rts1 and rts0 pins can be defined by bits rtse1[3:0] 12h[7:4] and rtse0[3:0] 12h[3:0]. symbol pin i/o description bit amclk 37 o audio master clock output without use of cgc2 acpf[17:0] (32h[1:0] 31h[7:0] 30h[7:0]), acni[21:0] (36h[5:0] 35h[7:0] 34h[7:0]), amvr (3ah[2]), apll (3ah[3]), ucgc (3ah[3]; must be set to 0) audio master clock output using of cgc2 (low jitter audio clock) acpf[17:0] (32h[1:0] 31h[7:0] 30h[7:0]), acni[21:0] (36h[5:0] 35h[7:0] 34h[7:0]), amvr (3ah[2]), apll (3ah[3]), ucgc (3ah[3]; must be set to 1), cgcdiv (3ah[6]) amxclk 41 i external audio master clock input for the clock division circuit, can be directly connected to output amclk for standard applications - asclk 39 o serial audio clock output, can be synchronized to rising or falling edge of amxclk sdiv[5:0] (38h[5:0]), scph (3ah[0]), alrclk 40 o audio channel (left/right) clock output, can be synchronized to rising or falling edge of asclk. lrdiv[5:0] (39h[5:0]), lrph(3ah[1]) i strapping during reset determines the crystal oscillator frequency to be used. -
preliminary nda required con?dential - nda required page 92 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 34 clock and real-time synchronization signals 9.4 video expansion port (x-port) the expansion port can be used either to output eight or ten bit video from the combfilter decoder directly or to receive video data from other external digital video sources such as mpeg decoder for output at the image port (i-port) whilst. the expansion port consists of three main groupings of signals: 8-bit dithered or 10-bit data output of component video y-c b -c r 4 : 2 : 2, i.e. in c b -y-c r -y, sequence. in 10-bit wide video mode the two data lsbs are output on the xrh and xrv signal lines. exceptionally raw video samples (e.g. adc test). 8-bit data input of component video y-c b -c r 4:2:2, i.e. c b -y-c r -y, byte serial. in input mode optionally the data bus can be extended to 16-bit by pins hpd7 to hpd0. in this mode xpd [7:0] carries the luminance data and hpd [7:0] carries the chrominance data. clock, synchronization and auxiliary i/o signals, accompanying the data stream. the data transfers through the expansion port represent a single d1 port, with half duplex mode. the sav and eav codes may be inserted optionally for data input (controlled by bit xcode (92h[3])). the input/output direction is switched for complete fields only. symbol pin i/o description bit crystal oscillator xtali 7 i input for crystal oscillator or reference clock - xtalo 6 o output of crystal oscillator - xtout 4 o reference (crystal) clock output drive (optional) xtoute (14h[3]) real-time signals (rt port) llc 28 o line-locked clock, nominal 27 mhz, double pixel clock locked to the selected video input signal, for backward compatibility only, do not use for new applications - llc2 29 o line-locked pixel clock, nominal 13.5 mhz, for backward compatibility only, do not use for new applications - rtco 36 o real-time control output, transfers real-time status information supporting rtc level 3.1 (see document rtc functional description, available on request) - i strapping during reset determines the i 2 c read/write addresses address. - rts0 34 o real-time status information line 0, can be programmed to carry various real-time information (see table 70) rtse0[3:0] (12h[3:0]) rts1 35 o real-time status information line 1, can be programmed to carry various real-time information (see table 71) rtse1[3:0] (12h[7:4])
preliminary nda required con?dential - nda required page 93 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 35 signals dedicated to the expansion port symbol pin i/o description bit xpd7 to xpd0 81, 82, 84 -87, 89, 90 i/o x-port data: in output mode controlled by decoder section, data format see table 36; in input mode y-cb-cr 4:2:2 ser ial input data or luminance part of a 16-bit y-cb-cr 4:2:2 data stream ofts[3:0] (1bh[4], 13h[2:0]), conlv (91h[7], c1h[7]), hldfv (91h[6], c1h[6]), scsrc[1:0] (91h[5:4], c1h[5:4]), scrqe (91h[3], c1h[3]), fsc[2:0] (91h[2:0], c1h[2:0]) hpd7 to hpd0 64 -67, 69 - 72 i/(o) with the x-port, these signals are used as input only, for 16-bit y-cb-c r4:2:2 video data. in this case hpd[7:0] carries chrominance data. icks[3:0] (80h[3:0]), scsrc[1:0] (91h[5:4], c1h[5:4]) xclk 94 i/o clock at expansion port: if output, then copy of llc; as input normally a double pixel clock of up to 32 mhz or a gated clock (clock gated with a quali?er) xcks (92h[0], c2h[0]) xdq 95 i/o data valid ?ag of the expansion port input (quali?er): if output, then decoder (href and vgate) gate (see fig.24) - xrdy 96 o data request ?ag = ready to receive, to work with optional buffer in external device, to prevent internal buffer over?ow; second function: input related task ?ag a/b xrqt (83h[2]) xrh 92 i/o horizontal reference signal for the x-port: as output: href or hs from the decoder (see fig.24) or bit 1 of d1 decoder 10 bit output; as input: a reference edge for horizontal input timing and a polarity for input ?eld id detection can be de?ned xrhs (13h[6]), xfdh (92h[6], c2h[6]), xdh (92h[2], c2h[2]] xrv 91 i/o vertical reference signal for the x-port: as output: v123 or ?eld id from the decoder, see figs 22 and or 23 or bit 0 of d1 decoder 10 bit output; as input: a reference edge for vertical input timing and for input ?eld id detection can be de?ned xrvs[1:0] (13h[5:4]), xfdv (92h[7], c2h[7]), xdv[1:0] (92h[5:4], c2h[5:4]) xtri 80 i port control: switches x-port input 3-state xpe[1:0] (83h[1:0])
preliminary nda required con?dential - nda required page 94 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 9.4.1 x- port configured as output if data output is enabled at the expansion port, then the data stream from the decoder is presented. the data format of the 8-bit data bus is dependent on the chosen data type, selectable by the line control registers lcr2 to lcr24; see table 6. in contrast to the image port, the sliced data format is not available on the expansion port. instead, raw cvbs samples are always transferred if any sliced data type is selected. some details of data types on the expansion port are as follows: active video (data types 0 and 15): contains component y-c b -c r 4:2:2 signal, 720 active pixels per line. the amplitude and offsets are programmable via dbri7 to dbri0, dcon7 to dcon0, dsat7 to dsat0, offu1, offu0, offv1 and offv0. for nominal levels see fig.18. test line (data type 14): is similar to the active video format, with some constraints within the data processing: C adaptive chrominance comb ?lter, vertical ?lter (chrominance comb ?lter for ntsc standards, pal phase error correction) within the chrominance processing are disabled C adaptive luminance comb filter, peaking and chrominance trap are bypassed within the luminance processing this data type is defined for future enhancements. it could be activated for lines containing standard test signals within the vertical blanking period. currently the most sources do not contain test lines. for nominal levels see fig.18. raw samples (data types 1 to 13): c b -c r samples are similar to data type 6, but cvbs samples are transferred instead of processed luminance samples within the y time slots. the amplitude and offset of the cvbs signal is programmable via rawg7 to rawg0 and rawo7 to rawo0; see chapter 16, tables 78 and 79. for nominal levels see fig.19. the relationship of lcr programming to line numbers is described in section 8.4, see tables 7 to 10. the data type selections by lcr are overruled by setting ofts[3:0] = 1110 (adc1 bypass mode) or ofts[3:0] = 1111 (adc2 bypass mode) at subaddresses 1bh, bit 4 and 13h bit 2 to 0. this setting is mainly intended for device production test. the x-port (xpd[7:0]) carries the upper 8 bits of either of the two adcs, the lsb is provided on pin xrh; see table 72 rt / x-port output control (sa 13, sa 1b). the analog input configuration is done via mode[3:0] 02h[3:0] settings; see table 53 analog control 1 (sa 02). no timing reference codes are generated in this mode. the sav/eav timing reference codes define the start and end of valid data regions. the itu-blanking code sequence - 80 - 10 - 80 - 10 -... is transmitted during the horizontal blanking period between eav and sav. the position of the f-bit is constant in accordance with itu 656; see tables 38 and 39. the v-bit can be generated in two different ways (see tables 38 and 39) controlled via ofts1 and ofts0; see table 72. in case of enabling 10-bit video output mode via ofts[3:0] then xpd[7:0] carries the video data bits 9 to 2 and sav/eav codes and the signals xrh and xrv the data lsbs 1 and 0 respectively. during blanking both lsbs are zero. the f and v bits change synchronously with the eav code. table 36 data format on the expansion port notes 1. the generation of the timing reference codes and the itu-blanking code sequence can be suppressed by setting ofts[3:0] to x010, see table 72. 2. if raw samples or sliced data are selected by the line control registers (lcr2 to lcr24), the y samples are replaced by cvbs samples. blanking period timing reference code (hex) (1) 720 pixels y-c b -c r 4:2:2 data (2) timing reference code (hex) (1) blanking period ... 80 10 ff 00 00 sav cb 0 y0 cr 0 y1 cb 2 y2 ... cr71 8 y719 ff 00 00 eav 80 10 ...
preliminary nda required con?dential - nda required page 95 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 37 format of the control byte of sav/eav codes on expansion port xpd7 to xpd0 table 38 525 lines/60 hz vertical timing table 39 625 lines/50 hz vertical timing bit 7 bit 6 (f) bit 5 (v) bit 4 (h) bit 3 (p3) bit 2 (p2) bit 1 (p1) bit 0 (p0) 1 ?eld bit vertical blanking bit format reserved; evaluation not recommended (protection bits according to itu 656) 1st field: f = 0 2nd field: f = 1 vbi: v = 1 active video: v = 0 h = 0 in sav format h = 1 in eav format for vertical timing see tables 38 and 39 line number f (itu 656) v ofts[3:0] = 0000 or ofts[3:0] = 1000 (itu 656) ofts[3:0] = 0001 or ofts[3:0] = 1001 1 to 3 1 1 according to selected vgate position type via vsta and vsto (subaddresses 15h to 17h); see tables 75 to 76 4to19 0 1 20 0 0 21 0 0 22 to 261 0 0 262 0 0 263 0 0 264 and 265 0 1 266 to 282 1 1 283 1 0 284 1 0 285 to 524 1 0 525 1 0 line number f (itu 656) v ofts[3:0] = 0000 or ofts[3:0] = 1000 (itu 656) ofts[3:0] = 0001 or ofts[3:0] = 1001 1 to 22 0 1 according to selected vgate position type via vsta and vsto (subaddresses 15h to 17h); see tables 75 to 76 23 0 0 24 to 309 0 0 310 0 0 311 and 312 0 1 313 to 335 1 1 336 1 0 337 to 622 1 0 623 1 0 624 and 625 1 1
preliminary nda required con?dential - nda required page 96 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 9.4.2 x- port configured as input if data input mode is selected at the expansion port, then the scaler can choose its input data stream from the on-chip video decoder, or from the expansion port (controlled by bit scsrc[1:0] (91h[5:4]), c1h[5:4])). byte serial y-c b -c r 4:2:2, or subsets for other sampling schemes, or raw samples from an external adc may be input (see also bits fsc[2:0] (91h[2:0], c1h[2:0])). the input stream must be accompanied by an external clock (xclk), qualifier xdq and reference signals xrh and xrv. instead of the reference signal, embedded sav and eav codes according to itu 656 are also accepted. the protection bits are not evaluated. xrh and xrv carry the horizontal and vertical synchronization signals for the digital video stream through the expansion port. the field id of the input video stream is carried in the phase (edge) of xrv and state of xrh, or directly as fs (frame sync, odd/even signal) on the xrv pin (controlled by xfdv (92h[7], c2h[7[), xfdh (92h[6], c2h[6]) and xdv[1:0] (92h[5:4], c2h[5:4])). the trigger events on xrh (rising/falling edge) and xrv (rising/falling/both edges) for the scalers acquisition window are defined by xdv[1:0] and xdh (92h[2], c2h[2]). the signal polarity of the qualifier can also be defined (bit xdq (92h[1], c2h[1])). alternatively to a qualifier, the input clock can be applied to a gated clock (means clock gated with a data qualifier, controlled by bit xcks (92h[0], c2h[0])). in this case, all input data will be qualified. in case if 16 bit wide data input is required for the x-port input then the hpd[7:0] port is enabled for input via scsrc[1:0] (91h[5:4], c1h[5:4]) whilst the i-port must be set to 8-bit output mode by icks[3:0] (80h[3:0]). 9.5 image port (i-port) the image port transfers data from the scaler as well as from the vbi-data slicer, if selected (maximum 33 mhz). the reference clock is available at the iclk pin, as an output, or as an input (maximum 33 mhz). as output, iclk is derived either from the line-locked decoder or from the expansion port input clock or from pll2/cgc2 combination, which enables square pixel clock generation feature. the data stream from the scaler output is usually discontinuous, which basically depends on the scale ratio. therefore valid data during a clock cycle is accompanied by a data qualifying (data valid) flag on pin idq. for pin constrained applications the idq pin can be programmed to function as a gated clock output (bit icks2[80h[2]]). the pulsegenerator allows however to squeeze all pixels of a video line so that a continuous video stream at the i-port output is obtained. for details refer to chapter 8.2.. the data formats at the image port are defined in dwords of 32 bits (4 bytes), such as the related fifo structures. however the physical data stream at the image port is only 16-bit or 8-bit wide; in 16-bit mode data pins hpd7 to hpd0 are used for chrominance data. the four bytes of the dwords are serialized in words or bytes. available formats are as follows: y-c b -c r 4:2:2 y-c b -c r 4:1:1 raw samples decoded vbi-data. for handshake with the receiving vga controller, or other memory or bus interface circuitry, f, h and v reference signals and programmable fifo flags are provided. the information is provided on pins igp0, igp1, igph and igpv. the functionality on these pins is controlled via subaddresses 84h and 85h. vbi-data is collected over an entire line in its own fifo, and transferred as an uninterrupted block of bytes. decoded vbi-data can be indicated by the vbi flag on pin igp0 or igp1. as scaled video data and decoded vbi-data may come from different and asynchronous sources, an arbitration scheme is needed. normally the vbi-data slicer has priority. the image port consists of the pins and/or signals, as listed in table 40.
preliminary nda required con?dential - nda required page 97 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 for pin constrained applications, or interfaces, the relevant timing and data reference signals can also be encoded into the data stream. therefore the corresponding signal pins do not need to be connected. the minimum image port configuration requires 9 pins only, i.e. 8 pins for data including codes, and 1 pin for clock or gated clock. the inserted codes are defined in close relationship to the itu-r bt.656 (d1) recommendation, where possible. in the case of scaling and for cmod [80[7]] = 0, the following deviations from itu 656 recommendation are implemented at the SAA7115s image port interface: sav and eav codes are only present in those lines, where data is to be transferred, i.e. active video lines, or vbi raw samples, no codes for empty lines (=lines not covered by the scalers window definition) there may be more or less than 720 pixels between sav and eav depending on the scaler settings data content and the number of clock cycles during horizontal and vertical blanking is undefined, and may not be constant. to get a regular pattern in case of scaling, the internal trigger positions for data packing (see section 8.5.4.2.) need to be balanced. data stream may be interleaved with not-valid data, 00h codes or old data (see bit ins80 [93[6]]), but sav and eav 4-byte codes are not interleaved with not-valid data codes there may be an irregular pattern of not-valid data, or idq, and as a result, c b -y-c r -y is not in a fixed phase to a regular clock divider vbi raw sample streams are enveloped with sav and eav, like normal video decoded vbi-data is transported as ancillary (anc) data or enveloped with sav and eav (see bits sldom [5d[4:0]]), two modes: C direct decoded vbi-data bytes (8-bit), 00h and ffh codes may appear in the data block (violation to itu-r bt.656) C recoded vbi-data bytes (8-bit), 00h and ffh codes will be recoded to even parity codes 03h and fch to suppress invalid itu-r bt.656 codes. sliced vbi data are transferred as continuous packages with no empty cycles. the data codes 00h and ffh are suppressed (changed to 01h or feh respectively) in the active video stream, as well as in the vbi raw sample stream (vbi pass-through). optionally, the number range can be further limited (see bit illv [85[5]]). if the video data are not packed and itrdy = 1, due to the internal 32 bit wide backend fifo, valid data occur as 4 byte (8 bit output), respec. 2 byte (16 bit output) packages of valid data.
preliminary nda required con?dential - nda required page 98 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 40 signals dedicated to the image port 9.6 host port for 16-bit extension of video data i/o (h-port) the h-port pins hpd can be used for extension of the data i/o paths to 16-bit. for the x-port hpd[7:0] are used as 16-bit input extension where as the i-port uses hpd[7:0] as 16-bit output extension. the i-port has functional priority. if a 16 bit output mode is set via icks[3:2], see table 121 i-port and scaler backend clock selection (sa 80) the output drivers of the h-port are enabled depending on the i-port enable control. symbol pin i/o description bit ipd7 to ipd0 54 -57, 59 -62 i/o i-port data icode (93h[7], c3h(7)), iswp[1:0] (85h[7:6]), ipe[1:0] (87h[1:0]) hpd7 to hpd0 64 -67, 69 - 72 (i)/o with the i-port, these signals are used as output only, for 16-bit y-cb-cr 4:2:2 video data. in this case hpd[7:0] carries chrominance data. icks[3:0] (80h[3:0]), scsrc[1:0] (91h[5:4], c1h[5:4]), ipe[1:0] (87h[1:0]) iclk 45 i/o continuous reference clock at image port, can be input or output, as output decoder llc or xclk from x-port icks[3:0] (80h[3:0]), ipe[1:0] (87h[1:0]) idq 46 o data valid ?ag at image port, quali?er, with programmable polarity; secondary function: gated clock icks[3:0] (80h[3:0]), ipe[1:0] (87h[1:0]) idqp[85h[0]] igph 53 o horizontal reference output signal, copy of the h-gate signal of the scaler, with programmable polarity; alternative function: hreset pulse idh[1:0] (84h[1:0]), irhp(85h[1]), ipe[1:0] 87h[1:0] igpv 52 o vertical reference output signal, copy of the v-gate signal of the scaler, with programmable polarity; alternative function: vreset pulse idv[1:0] 84h[3:2], irvp (85h[2]), ipe[1:0] (87h[1:0]) igp1 49 o general purpose output signal for i-port idg12 (86h[4]), idg1[1:0] (84h[5:4]), ig1p (85h[3]), ipe[1:0] (87h[1:0]) igp0 48 o general purpose output signal for i-port idg02 (86h[5]), idg0[1:0] (84h[7:6]), ig0p (85h[4]), ipe[1:0] (87h[1:0]) itrdy 42 i target ready input signals - itri 47 i port control, switches i-port into 3-state ipe[1:0] (87h[1:0])
preliminary nda required con?dential - nda required page 99 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 41 signals dedicated to the host port 9.7 basic input and output timing diagrams i-port and x-port 9.7.1 i- port output timing the following diagrams (figures 33 to 39) illustrate the output timing via the i-port. igph and the scalers igpv are logic 1 active gate signals. if reference pulses are programmed, these pulses are generated on the rising edge of the logic 1 active gates. valid data is accompanied by the output data qualifier on pin idq. an data request via itrdy = 1 is answered with the next clock cycle by marking this cycle as valid or invalid data. due to the scaling and the output processing, it may last several itrdy = 1 cycles, before a request is answered with valid data. after running in and if the requested data rate is matched to the scaled data rate, valid data are normally provided with the next clock cycle. the behaviour during invalid clock cycles depend on the ins80 bit and the itrdy input. for ins80 = 0 the value 00h is inserted on ipd[7:0], resp. hpd[7:0], for all clock cycles marked with idq = 0 for ins80 = 1 data are hold during a line, if itrdy =0 or idq=0. outside the active line and in 8 bit output mode, the inserted blanking values (80h, 10h) change with every itrdy = 1. as there are now internal counters for data packing implemented (see sect. 8.5.4.2 and parameters pghaps, pghbps and pghcps), the itrdy packing is mainly useful for burst data transfers. the idq output pin may be defined to be a gated clock output signal (iclk and internal idq). 9.7.2 x- port input timing at the x-port the input timing requirements are the same as those for the i-port output. but different to those below: it is not necessary to mark invalid cycles with a 00h code no constraints on the input qualifier (can be a random pattern) xclk may be a gated clock (xclk and external xdq). remark : all timings illustrated in figures 33 to 39 are given for an uninterrupted output stream (no handshake with the external hardware). symbol pin i/o description bit hpd7 to hpd0 64 -67, 69 - 72 i/(o) with the x-port, these signals are used as input only, for 16-bit y-cb-c r4:2:2 video data. in this case hpd[7:0] carries chrominance data. icks[3:0] (80h[3:0]), scsrc[1:0] (91h[5:4], c1h[5:4]), ipe[1:0] (87h[1:0]), itri ([8fh[6]) (i)/o with the i-port, these signals are used as output only, for 16-bit y-cb-c r4:2:2 video data. in this case hpd[7:0] carries chrominance data.
preliminary nda required con?dential - nda required page 100 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 iclk fig.33 output timing i-port for serial 8 bit data (icode = 1, ins80 = 0) idq ipd[7:0] igph cb y cb cr y y cr ff 00 00 sav 00 00 00 ff 00 00 eav 00 iclk fig.34 output timing i-port for serial 8 bit data (icode = 0, ins80 = 0) idq ipd[7:0] igph cb y cb cr y y cr 00 00 00
preliminary nda required con?dential - nda required page 101 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 iclk fig.35 output timing i-port for serial 8 bit data (icode = 1, ins80 = 1) idq ipd[7:0] igph cb y cb cr y y cr ff 00 00 sav 10(80) ff 00 00 eav 80 10 iclk fig.36 output timing i-port using the itrdy pin (icode = 1) itrdy ipd[7:0] ff 00 y 00 cr 80 idq r p nr r p nr = request new data = no request = new data are placed r r r r r r r r nr nr nr nr h = hold data h p h h p p p igph p p idq = 1 and igph = 0 = sav or eav sequence h p h h nr r h nr h y eav 10
preliminary nda required con?dential - nda required page 102 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 iclk fig.37 output timing for 16 bit data output via i-port and h-port with codes (icode = 1, ins80 = 0), timing is like 8 bit output, but packages of 2 bytes per valid cycle idq ipd[7:0] igph y2 00 ff y3 y1 y n-1 y0 y n ff 00 hpd[7:0] cb sav 00 cr cr cb cb cr 00 eav 00 00 00 00 00 00 00 00 00 00 idq fig.38 the scalers h-gate and v-gate output timing igph igpv
preliminary nda required con?dential - nda required page 103 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 iclk fig.39 output timing for sliced vbi data in 8 bit serial output mode (for ins80 = 1) idq ipd[7:0] sliced data flag xx yy bc cs zz 10 80 00 ff ff did 10 sdid 80 ff 00 00 sav 00 ff 00 00 eav bc on igp0 or igp1 10 80
preliminary nda required con?dential - nda required page 104 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 10 boundary scan test the SAA7115 has built-in logic and 5 dedicated pins to support boundary scan testing which allows board testing without special hardware (nails). the SAA7115 follows the ieee std. 1149.1 - standard test access port and boundary-scan architecture set by the joint test action group (jtag) chaired by philips. the 5 special pins are test mode select (tms), test clock (tck), test reset (trstn), test data input (tdi) and test data output (tdo). the boundary scan test (bst) functions bypass, extest, intest, sample, clamp and idcode are all supported (see table 42). details about the jtag bst-test can be found in specification ieee std. 1149.1 . a file containing the detailed boundary scan description language (bsdl) description of the SAA7115 is available on request. table 42 bst instructions supported by the SAA7115 10.1 initialization of boundary scan circuit the tap (test access port) controller of an ic should be in the reset state (test_logic_reset) when the ic is in functional mode. this reset state also forces the instruction register into a functional instruction such as idcode or bypass. to solve the power-up reset, the standard specifies that the tap controller will be forced asynchronously to the test_logic_reset state by setting the trstn pin low. 10.2 device identi?cation codes a device identification register is specified in ieee std. 1149.1b-1994 . it is a 32-bit register which contains fields for the specification of the ic manufacturer, the ic part number and the ic version number. its biggest advantage is the possibility to check for the correct ics mounted after production and determination of the version number of ics during field service. when the idcode instruction is loaded into the bst instruction register, the identification register will be connected between tdi and tdo of the ic. the identification register will load a component specific code during the capture_data_register state of the tap controller and this code can subsequently be shifted out. at board level this code can be used to verify component manufacturer, type and version number. the device identification register contains 32 bits, numbered 31 to 0, where bit 31 is the most significant bit (nearest to tdi) and bit 0 is the least significant bit (nearest to tdo); see fig.40. instruction description bypass this mandatory instruction provides a minimum length serial path (1 bit) between tdi and tdo when no test operation of the component is required. extest this mandatory instruction allows testing of off-chip circuitry and board level interconnections. sample this mandatory instruction can be used to take a sample of the inputs during normal operation of the component. it can also be used to preload data values into the latched outputs of the boundary scan register. clamp this optional instruction is useful for testing when not all ics have bst. this instruction addresses the bypass register while the boundary scan register is in external test mode. idcode this optional instruction will provide information on the components manufacturer, part number and version number. intest this optional instruction allows testing of the internal logic (no customer support available). user1 this private instruction allows testing by the manufacturer (no customer support available).
preliminary nda required con?dential - nda required page 105 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 handbook, full pagewidth mhb734 00000010101 0111000100011000 nnnn 4-bit version code 16-bit part number 11-bit manufacturer identification tdi tdo 31 msb lsb 28 27 12 11 1 0 1 fig.40 32 bits of identification code. 0111 0001 0001 0101
preliminary nda required con?dential - nda required page 106 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 11 limiting values table 43 limiting values 12 thermal characteristics table 44 thermal characteristics symbol parameter conditions min max unit vddx supply voltage digital -0.5 +4.6 v vddax supply voltage analog -0.5 +4.6 v via input voltage at analog inputs note 3 -0.5 vdda + 0.5 (4.6 max) v voa output voltage at analog output -0.5 vdda + 0.5 v vid input voltage at digital inputs outputs in tristate, note 2, 3 -0.5 +5.5 v vod output voltage at digital outputs outputs active -0.5 vddx + 0.5 v vdiffgnd difference voltage between vssaall and vssall - 100 mv tstg storage temperature -65 +150 c tamb operating ambient temperature range 0 +70 c vesd electrostatic handling for all pins note 1 -2000 +2000 v note 1. equivalent to discharging a 100pf capacitor through an 1.5kw series resistor (human body model) 2. with the exception of pin xtali 3. the chip must be supplied correctly with at least the minimum supply voltage of 3.0v symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 52.5 k/w
preliminary nda required con?dential - nda required page 107 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 13 characteristics table 45 characteristics v ddd = 3.0 to 3.6 v; v dda = 3.1 to 3.5 v; t amb =25 c; timings and levels refer to drawings and conditions illustrated in fig.41; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies v ddd digital supply voltage 3.0 3.3 3.6 v i ddd digital supply current x-port 3-state; 8-bit i-port - tbd. - ma p d power dissipation digital part - tbd. - mw v dda analog supply voltage 3.1 3.3 3.5 v i dda analog supply current aosl1 and aosl0 = 0 cvbs mode - tbd. - ma y/c mode - tbd. - ma component mode - tbd. - ma p a power dissipation analog part cvbs mode - tbd. - mw y/c mode - tbd. - mw component mode - tbd. - mw p tot(a+d) total power dissipation analog and digital part cvbs mode - tbd. - mw y/c mode - tbd. - mw p tot(a+d)(pd) total power dissipation analog and digital part in power-down mode ce pulled down to ground - tbd. - mw p tot(a+d)(ps) total power dissipation analog and digital part in power-save mode i 2 c-bus controlled via subaddress 88h - tbd. - mw p tot(a+d)(ps) total power dissipation analog and digital part in power-save mode controlled via chip enable input (ce, pin 27) - tbd. - mw analog part i clamp clamping current v i =1vdc - 8 -m a v i(p-p) input voltage (peak-to-peak value) for normal video levels 1 v (p-p), - 3 db termination 18/56 w and ac coupling required; coupling capacitor is 47 nf - 0.7 - v ? z i ? input impedance clamping current off 200 -- k w c i input capacitance -- 10 pf a cs channel crosstalk f i < 5 mhz --- 50 db
preliminary nda required con?dential - nda required page 108 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 9-bit analog-to-digital converters b analog bandwidth at - 3db - 7 - mhz f diff differential phase ampli?er plus anti-alias ?lter bypassed - 2 - deg g diff differential gain ampli?er plus anti-alias ?lter bypassed - 2 - % f clk(adc) adc clock frequency 25.4 - 28.6 mhz le dc(d) dc differential linearity error - 0.7 - lsb le dc(i) dc integral linearity error - 1 - lsb d g adc adc gain inequality note 1 - 3 - % digital inputs v il(scl,sda) low-level input voltage pins sda and scl note 2 - 0.5 - +0.3v dd(i2c) v v ih(scl,sda) high-level input voltage pins sda and scl note 2 0.7v dd(i2c) - v dd(i2c) + 0.5 v v il(xtali) low-level cmos input voltage pin xtali - 0.3 - +0.8 v v ih(xtali) high-level cmos input voltage pin xtali 2.0 - v ddd + 0.3 v v il(n) low-level input voltage all other inputs - 0.3 - +0.8 v v ih(n) high-level input voltage all other inputs 2.0 - 5.5 v i li input leakage current -- 1 m a i li/o i/o leakage current -- 10 m a c i input capacitance i/o at high-impedance -- 8pf digital outputs; note 3 v ol(sda) low-level output voltage pin sda sda at 3 ma sink current -- 0.4 v v ol(clk) low-level output voltage for clocks - 0.5 - +0.6 v v oh(clk) high-level output voltage for clocks 2.4 - v ddd + 0.5 v symbol parameter conditions min. typ. max. unit maximum deviation minimum deviation --------------------------------------------------- 1 C ? ?? 100
preliminary nda required con?dential - nda required page 109 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 v ol(n) low-level output voltage all other digital outputs 0 - 0.4 v v oh(n) high-level output voltage all other digital outputs 2.4 - v ddd + 0.5 v clock output timing (llc and llc2); note 4 c l output load capacitance 15 - 50 pf t cy cycle time pin llc 35 - 39 ns pin llc2 70 - 78 ns d duty factors t clkh /t cy c l =40pf 40 - 60 % t r rise time llc and llc2 0.2vtov ddd - 0.2 v -- 5ns t f fall time llc and llc2 v ddd - 0.2 v to 0.2 v -- 5ns t d(llc-llc2) delay time between llc and llc2 output measured at 1.5 v; c l =25pf tbd. - tbd. ns horizontal pll f hor(n) nominal line frequency 50 hz ?eld - 15625 - hz 60 hz ?eld - 15734 - hz d f hor /f hor(n) permissible static deviation -- 5.7 % subcarrier pll f sc(n) nominal subcarrier frequency pal bghi - 4433619 - hz ntsc m - 3579545 - hz pa l m - 3575612 - hz pa l n - 3582056 - hz d f sc lock-in range 400 -- hz crystal oscillator for 32.11 mhz; note 5 f xtal(nom) nominal frequency 3rd harmonic - 32.11 - mhz d f xtal(nom) permissible nominal frequency deviation -- 70 10 - 6 d f xtal(nom)(t) permissible nominal frequency deviation with temperature -- 30 10 - 6 c rystal specification (x1) t amb(x1) ambient temperature 0 - 70 c c l load capacitance 8 -- pf symbol parameter conditions min. typ. max. unit
preliminary nda required con?dential - nda required page 110 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 r s series resonance resistor - 40 80 w c 1 motional capacitance - 1.5 20% - ff c 0 parallel capacitance - 4.3 20% - pf crystal oscillator for 24.576 mhz; note 5 f xtal(n) nominal frequency 3rd harmonic - 24.576 - mhz d f xtal(n) permissible nominal frequency deviation -- 50 10 - 6 d f xtal(n)(t) permissible nominal frequency deviation with temperature -- 20 10 - 6 c rystal specification (x1) t amb(x1) ambient temperature 0 - 70 c c l load capacitance 8 -- pf r s series resonance resistor - 40 80 w c 1 motional capacitance - 1.5 20% - ff c 0 parallel capacitance - 3.5 20% - pf expansion port (x-port) output timing with xclk clock output t cy cycle time xclk output 35 - 39 ns c l output load capacitance 15 - 50 pf d duty factors for t xclkh /t xclkl tbd. - tbd. % t r rise time 0.6 to 2.6 v -- tbd. ns t f fall time 2.6 to 0.6 v -- tbd. ns data and control signal output timing x-port including rt port, related to xclk output (for xpck[1:0] 83h[5:4] = 11); note 4 c l output load capacitance 15 - 50 pf t ohd;dat output data hold time valid for outputs: xpd [7:0], xrh, xrv, xdq, rts0, rts1, rtco tbd. - - ns t pd propagation delay from positive edge of xclk output - - tbd. ns expansion port (x-port) input timing with xclk clock input t cyx xclk cycle time xclk input 31 - 45 ns symbol parameter conditions min. typ. max. unit
preliminary nda required con?dential - nda required page 111 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 d duty factor: t xclkh /t cy tbd. 50 tbd. % t r rise time -- 5ns t f fall time -- 5ns data and control signal input timing x-port, related to xclk input (for xpck[1:0] 83h[5:4] = 11); t su;dat input data set-up time valid for inputs: xpd [7:0], hpd [7:0], xrh, xrv, xdq tbd. - - ns t hd;dat input data hold time - - tbd. ns t ohd;dat output data hold time valid for output: xrdy tbd. - - ns t pd propagation delay from positive edge of xclk input - - tbd. ns image port (i-port) output timing with iclk clock output c l output load capacitance 15 - 50 pf t cy cycle time 31 - 90 ns d duty factor: t iclkh /t iclkl c l =40pf tbd. - tbd. % t r rise time 0.6 to 2.6 v -- 5ns t f fall time 2.6 to 0.6 v -- 5ns data and control signal output timing i-port, related to iclk output (for ipck[1:0] 87h[5:4] = 11) c l output load capacitance at all outputs 15 - 50 pf t ohd;dat output data hold time valid for outputs: ipd [7:0], hpd [7:0], igph, igpv, idq, igp1, igp0 tbd. - - ns t o(d) output delay time - - 23 ns data and control signal input timing i-port, related to iclk output (for ipck[1:0] 83h[5:4] = 11); t su;dat input data set-up time valid for input: itrdy 18 - - ns t hd;dat input data hold time - - tbd. ns image port (i-port) output timing with iclk clock input t cy cycle time 31 - 100 ns d duty factors: t iclkh /tcy tbd. 50 tbd. % t r rise time 0.6 to 2.6 v -- 5ns t f fall time 2.6 to 0.6 v -- 5ns data and control signal output timing i-port, related to iclk input (for ipck[1:0] 87h[5:4] = 11) symbol parameter conditions min. typ. max. unit
preliminary nda required con?dential - nda required page 112 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 notes 1. adc1 is not taken into account, since component video is always converted by adc2, adc3 and adc4. 2. v dd(i2c) is the supply voltage of the i 2 c-bus. for v dd(i2c) = 3.3 v is v il(scl,sda)(max) = 1 v; for v dd(i2c) = 5 v is v il(scl,sda)(max) = 1.5 v. for v dd(i2c) = 3.3 v is v ih(scl,sda)(min) = 2.3 v; for v dd(i2c) =5visv ih(scl,sda)(min) = 3.5 v. 3. the levels must be measured with load circuits; 1.2 k w at 3 v (ttl load); c l =50pf. 4. the effects of rise and fall times are included in the calculation of t ohd;dat and t pd . timings and levels refer to drawings and conditions illustrated in fig.41. 5. the crystal oscillator drive level is typical 0.28 mw. c l output load capacitance at all outputs 15 - 50 pf t ohd;dat output hold time valid for outputs: ipd [7:0], hpd [7:0], igph, igpv, idq, igp1, igp0 tbd. - - ns t pd propagation delay from positive edge of llc output - - tbd. ns data and control signal input timing i-port, related to iclk input (for ipck[1:0] 83h[5:4] = 11); t su;dat input data set-up time valid for input: itrdy tbd. - - ns t hd;dat input data hold time - - tbd. ns amclk clock output c l output load capacitance 15 - 50 pf t r rise time 0.6 to 2.6 v -- 5ns t f fall time 2.6 to 0.6 v -- 5ns symbol parameter conditions min. typ. max. unit
preliminary nda required con?dential - nda required page 113 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 handbook, full pagewidth mhb735 t xclkh t r t r t f t hd;dat t su;dat t su;dat t hd;dat t cy t x(i)clkh t x(i)clkl t f clock input xclk data and control inputs (x port) data and control outputs x port, i port clock outputs llc, llc2, xclk, iclk and iclk input input xdq 2.4 v 1.5 v 0.6 v - 2.6 v - 1.5 v - 0.6 v 2.0 v 0.8 v t ohd;dat t o(d) - 2.4 v - 0.6 v 2.0 v 0.8 v not valid fig.41 data input/output timing diagram (x-port, rt port and i-port).
preliminary nda required con?dential - nda required page 114 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 14 application information fig.42 application example ipd7 ipd1 ipd0 ipd4 ipd3 ipd6 ipd5 ipd2 bst0 bst1 bst2 imcon0 imcon5 imcon1 imcon3 ai22 ai21 ai12 ai11 ipd[0..7] resn sda ai23 ai24 tdi bst[0..2] tdo xpd[0..7] imcon[0..7] scl hpd[0..7] xcon[0..6] rcon[0..2] c2 47nf c3 47nf c4 47nf r5 18r r3 18r r2 18r c1 47nf c5 47nf c6 47nf r4 18r r1 18r r10 56r r11 56r r12 56r r13 56r r14 56r r15 56r r6 18r c10 10pf c11 10pf y1 32.11mhz c9 1nf l3 10h agnd dgnd imcon4 dgnd xpd0 xpd1 xpd2 xpd3 xpd4 xpd5 xpd6 xpd7 audio[0..3] 3v3d dgnd hpd0 hpd1 hpd2 hpd3 hpd4 hpd5 hpd6 hpd7 c7 47nf c8 47nf agnd agnd hpd[0..7] ipd[0..7] imcon[0..7] xpd[0..7] xcon[0..6] bst[0..2] 3v3d 3v3a agnd 3v3d rcon[0..2] rcon0 rcon1 rcon2 xcon0 xcon1 xcon2 xcon3 xcon4 xcon5 xcon6 imcon2 imcon6 imcon7 audio[0..3] audio0 audio1 audio2 audio3 'strapping' i2c slave address dgnd r7 33r r8 33r r9 33r 'strapping' clock frequency c25 100nf c24 100nf agnd c23 100nf c20 100nf c19 100nf c18 100nf c17 100nf c21 100nf c22 100nf c14 100nf c13 100nf c12 100nf dgnd c15 100nf c16 100nf r19 open r20 3k3 r17 0r 3v3a l2 ferrite l1 ferrite vddd vdda cp1 10f cp2 10f r16 0r r18 open 3v3d ipd7 54 igph 53 igp1 49 igp0 48 itri 47 idq 46 iclk 45 vsse 50 ipd0 62 ipd1 61 ipd3 59 ipd2 60 vddi 58 ipd4 57 ipd5 56 ipd6 55 aout 22 hpd4 67 vdde 51 vddi 43 rts1 35 llc 28 vdda2 11 ai2d 13 vssa1 15 vdda1 17 ai1d 19 agnd 21 xtali 7 vxdd 8 vssa2 9 rtco 36 amclk 37 vdde 25 ai12 18 ai22 14 ai24 10 vssi 63 itrdy 42 vssi 38 amxclk 41 vdda0 23 hpd6 65 hpd5 66 vddi 68 igpv 52 test0 44 rts0 34 ce 27 llc2 29 reson 30 scl 31 vsse 26 vddi 33 sda 32 alrclk 40 asclk 39 tdi 3 vssa0 24 ai11 20 ai21 16 ai23 12 tdo 2 vdde 1 xtout 4 vxss 5 xtal 6 hpd7 64 hpd3 69 hpd2 70 hpd1 71 hpd0 72 test1 73 test2 74 vdde 75 vsse 76 test3 77 test4 78 test5 79 xtri 80 xpd7 81 xpd6 82 vddi 83 xpd5 84 xpd4 85 xpd3 86 xpd2 87 vssi 88 xpd1 89 xpd0 90 xrv 91 xrh 92 vddi 93 xclk 94 xdq 95 xrdy 96 trstn 97 tck 98 tms 99 vsse 100 SAA7115hl u1 SAA7115 r21 4k7 connect to 3v3d or other control-signal SAA7115hl
preliminary nda required con?dential - nda required page 115 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 6 7 SAA7115 xtalo xtali 6 7 SAA7115 xtalo xtali 6 7 SAA7115 xtalo xtali 6 7 SAA7115 xtalo xtali 6 7 SAA7115 xtalo xtali 6 7 SAA7115 xtalo xtali 6 7 SAA7115 xtalo xtali (1a) with 3rd harmonic quartz. crystal load = 8 pf 4.7 m h 1nf 15 pf 15 pf 32.11 mhz (1b) with fundamental quartz. crystal load = 20 pf 39 pf 39 pf 32.11 mhz (1c) with fundamental quartz. crystal load = 8 pf 15 pf 15 pf 32.11 mhz (2a) with 3rd harmonic quartz. 4.7 m h 1nf 18 pf 18 pf 24.576 mhz (2b) with fundamental quartz. 39 pf 39 pf (2c) with fundamental quartz. 15 pf 15 pf (3a) with direct clock 24.576 mhz n.c. clock 32.11 mhz or 24.576 mhz 24.576 mhz (3b) with fundamental quartz crystal and restricted drive level. when pdrive of the internal oscillator is too high a resistance rs can be placed in series with the output of the oscillator xtalo. note: the decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease. rs 6 7 SAA7115 xtalo xtali fig.43 oscillator applications
preliminary nda required con?dential - nda required page 116 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 15 device programming overview 15.1 i2c-bus description table 46 description of i 2 c-bus format note 1. if pin rtco strapped to supply voltage via a 4.7 k w resistor. code description s start condition sr repeated start condition slave address w 0100 0010 (42h, default) or 0100 0000 (40h; note 1) slave address r 0100 0011 (43h, default) or 0100 0001 (41h; note 1) ack-s acknowledge generated by the slave ack-m acknowledge generated by the master subaddress subaddress byte; see tables 47 and 48 data data byte; see ?gure 44; if more than one byte data is transmitted the subaddress pointer is automatically incremented p stop condition x read/write control bit (lsb slave address); x = 0, order to write (the circuit is slave receiver); x = 1, order to read (the circuit is slave transmitter) ack-s ack-s data slave address w data transferred (n bytes + acknowledge) mhb339 p s ack-s subaddress a. write procedure. b. read procedure (combined). ack-s ack-m slave address r mhb340 p sr ack-s ack-s data subaddress slave address w s data transferred (n bytes + acknowledge) fig.44 i 2 c-bus format.
preliminary nda required con?dential - nda required page 117 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 15.2 register overview table 47 subaddress description and access subaddress description access (read/write) 00h chip version read only video decoder: 01h to 2fh 01h to 05h front-end part read and write 06h to 19h decoder part read and write 1ah to 1dh color decoding, misc read and write 1eh to 1fh video decoder status byte read only 20h to 2fh reserved - audio clock generation: 30h to 3fh 30h to 3ah audio clock generator read and write 3bh to 3fh reserved - general purpose vbi-data slicer: 40h to 7fh 40h to 5bh vbi-data slicer read and write 5ch reserved - 5dh to 5eh vbi-data slicer read and write 5fh reserved - 60h to 65h vbi-data slicer status read only 66h to 7fh i 2 c readback of sliced vbi data read only x-port, i-port, scaler and power save control: 80h to efh 80h to 8fh task independent global settings read and write 90h to bfh task a de?nition read and write c0h to efh task b de?nition read and write second pll (pll2) and pulsegenerator: f0h to ffh f0h to f4h second pll settings read and write f5h to fbh pulsegenerator read and write fch to feh reserved read and write ffh second pll, lock status de?nition read and write
preliminary nda required con?dential - nda required page 118 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 48 i 2 c-subaddress overview (1) register function sub addr d7 d6 d5 d4 d3 d2 d1 d0 register 00 to 2f used by chip version part chip version (read only) 00 id7 id6 id5 id4 id3 id2 id1 id0 registers 01 to 1f used by the video decoder part increment delay 01 aosl2 wpoff gudl1 gudl0 idel3 idel2 idel1 idel0 analog input control 1 02 fuse1 fuse0 0 0 mode3 mode2 mode1 mode0 analog input control 2 03 test hlnrs vbsl cpoff holdg gafix gai28 gai18 analog input control 3 04 gai17 gai16 gai15 gai14 gai13 gai12 gai11 gai10 analog input control 4 05 gai27 gai26 gai25 gai24 gai23 gai22 gai21 gai20 horizontal sync start 06 hsb7 hsb6 hsb5 hsb4 hsb3 hsb2 hsb1 hsb0 horizontal sync stop 07 hss7 hss6 hss5 hss4 hss3 hss2 hss1 hss0 sync control 08 aufd fsel foet htc1 htc0 hpll vnoi1 vnoi0 luminance control 09 byps ycomb ldel lubw lufi3 lufi2 lufi1 lufi0 luminance brightness adjustment 0a dbri7 dbri6 dbri5 dbri4 dbri3 dbri2 dbri1 dbri0 luminance contrast adjustment 0b dcon7 dcon6 dcon5 dcon4 dcon3 dcon2 dcon1 dcon0 chroma saturation adjustment 0c dsat7 dsat6 dsat5 dsat4 dsat3 dsat2 dsat1 dsat0 chroma hue control 0d huec7 huec6 huec5 huec4 huec3 huec2 huec1 huec0 chroma control 1 0e cdto cstd2 cstd1 cstd0 dcvf fctc auto0 ccomb chroma gain control 0f acgc cgain6 cgain5 cgain4 cgain3 cgain2 cgain1 cgain0 chroma control 2 10 offu1 offu0 offv1 offv0 chbw lcbw2 lcbw1 lcbw0 mode/delay control 11 colo rtp1 hdel1 hdel0 rtp0 ydel2 ydel1 ydel0 rt signal control 12 rtse13 rtse12 rtse11 rtse10 rtse03 rtse02 rtse01 rtse00 rt / x-port output control 13 rtce xrhs xrvs1 xrvs0 hlsel ofts2 ofts1 ofts0 analog / adc / compatibility control 14 cm99 uptcv aosl1 aosl0 xtoute auto1 apck1 apck0 vgate start, fid change 15 vsta7 vsta6 vsta5 vsta4 vsta3 vsta2 vsta1 vsta0 vgate stop 16 vsto7 vsto6 vsto5 vsto4 vsto3 vsto2 vsto1 vsto0 (1) colour codes in this table: - green: new or modi?ed functionality (related to all previous decoder designs), - yellow: new or modi?ed functionality already realized in saa7118 (where SAA7115 is mainly derived from) - red: hidden functionality
preliminary nda required con?dential - nda required page 119 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 misc / vgate msbs 17 llce llc2e laty2 laty1 laty0 vgps vsto8 vsta8 raw data gain 18 rawg7 rawg6 rawg5 rawg4 rawg3 rawg2 rawg1 rawg0 raw data offset 19 rawo7 rawo6 rawo5 rawo4 rawo3 rawo2 rawo1 rawo0 colorkiller thresholds 1a qthr3 qthr2 qthr1 qthr0 sthr3 sthr2 sthr1 sthr0 misc /tvvcrdet 1b atvt1 atvt0 0 ofts3 0 0 acol fsqc enhanced comb ctrl1 1c hodg1 hodg0 vedg1 vedg0 medg1 medg0 cmbt1 cmbt0 enhanced comb ctrl2 1 d 0 0 0 0 0 0 vedt1 vedt0 status byte decoder 1 (read only) 1e nfld hlck sltca glimt glimb wipa dcstd1 dcstd0 status byte decoder 2 (read only) 1f intl hlvln fidt sttb type3 colstr copro rdcap registers 20 to 2f reserved for future extensions (e.g. component processing saa7118+) reserved 20 to 2f 0 0 0 0 0 0 0 0 registers 30 to 3f used by audio clock generator audio master clock cycles per field 30 acpf7 acpf6 acpf5 acpf4 acpf3 acpf2 acpf1 acpf0 audio master clock cycles per field 31 acpf15 acpf14 acpf13 acpf12 acpf11 acpf10 acpf9 acpf8 audio master clock cycles per field 32 0 0 0 0 0 0 acpf17 acpf16 reserved for future extensions 3300000000 audio master clock nominal increment 34 acni7 acni6 acni5 acni4 acni3 acni2 acni1 acni0 audio master clock nominal increment 35 acni15 acni14 acni13 acni12 acni11 acni10 acni9 acni8 audio master clock nominal increment 36 0 0 acni21 acni20 acni19 acni18 acni17 acni16 reserved for future extensions 3700000000 clock ratio amxclk to asclk 38 0 0 sdiv5 sdiv4 sdiv3 sdiv2 sdiv1 sdiv0 clock ratio asclk to alrclk 39 0 0 lrdiv5 lrdiv4 lrdiv3 lrdiv2 lrdiv1 lrdiv0 audio clock gen. basic setup 3a ucgc cgcdiv 0 0 apll amvr lrph scph reserved 3b to 3f 0 0 0 0 0 0 0 0 registers 40 to 7f used by general purpose vbi data slicer ac1 40 chkwss ham_n fce hunt_n 0 0 0 0 lcr2 41 lcr02_7 lcr02_6 lcr02_5 lcr02_4 lcr02_3 lcr02_2 lcr02_1 lcr02_0 register function sub addr d7 d6 d5 d4 d3 d2 d1 d0
preliminary nda required con?dential - nda required page 120 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 lcr3 42 lcr03_7 lcr03_6 lcr03_5 lcr03_4 lcr03_3 lcr03_2 lcr03_1 lcr03_0 ... ... ... ... ... ... ... ... ... ... lcr23 56 lcr23_7 lcr23_6 lcr23_5 lcr23_4 lcr23_3 lcr23_2 lcr23_1 lcr23_0 lcr24 57 lcr24_7 lcr24_6 lcr24_5 lcr24_4 lcr24_3 lcr24_2 lcr24_1 lcr24_0 fc 58 fc7 fc6 fc5 fc4 fc3 fc2 fc1 fc0 hoff 59 hoff7 hoff6 hoff5 hoff4 hoff3 hoff2 hoff1 hoff0 voff 5a voff7 voff6 voff5 voff4 voff3 voff2 voff1 voff0 hvoff 5b foff 0 vep voff8 0 hoff10 hoff9 hoff8 reserved 5c 0 0 0 0 0 0 0 0 sliced data output mode 5d 00 0 sldom4 sldom3 sldom2 sldom1 sldom0 d7,d6 are read only, 2nd text data ident. code sdid 5e fc8v fc7v sdid5 sdid4 sdid3 sdid2 sdid1 sdid0 reserved 5f 0 0 0 0 0 0 0 0 reserved (dont use) 65 - - - - - - - - i2c-readback 1 cc-header 66 cch_7 cch_6 cch_5 cch_4 cch_3 cch_2 cch_1 cch_0 i2c-readback 2 cc-odd byte 1 67 cco1_7 cco1_6 cco1_5 cco1_4 cco1_3 cco1_2 cco1_1 cco1_0 i2c-readback 3 cc-odd byte 2 68 cco2_7 cco2_6 cco2_5 cco2_4 cco2_3 cco2_2 cco2_1 cco2_0 i2c-readback 4 cc-even byte 1 69 cce1_7 cce1_6 cce1_5 cce1_4 cce1_3 cce1_2 cce1_1 cce1_0 i2c-readback 5 cc-even byte 2 6a cce2_7 cce2_6 cce2_5 cce2_4 cce2_3 cce2_2 cce2_1 cce2_0 i2c-readback 6 wss-header 6b wssh_7 wssh_6 wssh_5 wssh_4 wssh_3 wssh_2 wssh_1 wssh_0 i2c-readback 7 wss-odd byte 1 6c wsso1_7 wsso1_6 wsso1_5 wsso1_4 wsso1_3 wsso1_2 wsso1_1 wsso1_0 i2c-readback 8 wss-odd byte 2 6d wsso2_7 wsso2_6 wsso2_5 wsso2_4 wsso2_3 wsso2_2 wsso2_1 wsso2_0 i2c-readback 9 wss-odd byte 3 6e wsso3_7 wsso3_6 wsso3_5 wsso3_4 wsso3_3 wsso3_2 wsso3_1 wsso3_0 i2c-readback 10 wss-even byte 1 6f wsse1_7 wsse1_6 wsse1_5 wsse1_4 wsse1_3 wsse1_2 wsse1_1 wsse1_0 i2c-readback 11 wss-even byte 2 70 wsse2_7 wsse2_6 wsse2_5 wsse2_4 wsse2_3 wsse2_2 wsse2_1 wsse2_0 i2c-readback 12 wss-even byte 3 71 wsse3_7 wsse3_6 wsse3_5 wsse3_4 wsse3_3 wsse3_2 wsse3_1 wsse3_0 i2c-readback 13 gs1-header 72 gs1h_7 gs1h_6 gs1h_5 gs1h_4 gs1h_3 gs1h_2 gs1h_1 gs1h_0 i2c-readback 14 gs1-odd 1 73 gs1o1_7 gs1o1_6 gs1o1_5 gs1o1_4 gs1o1_3 gs1o1_2 gs1o1_1 gs1o1_0 register function sub addr d7 d6 d5 d4 d3 d2 d1 d0
preliminary nda required con?dential - nda required page 121 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 i2c-readback 15 gs1-odd 2 74 gs1o2_7 gs1o2_6 gs1o2_5 gs1o2_4 gs1o2_3 gs1o2_2 gs1o2_1 gs1o2_0 i2c-readback 16 gs1-even 1 75 gs1e1_7 gs1e1_6 gs1e1_5 gs1e1_4 gs1e1_3 gs1e1_2 gs1e1_1 gs1e1_0 i2c-readback 17 gs1-even 2 76 gs1e2_7 gs1e2_6 gs1e2_5 gs1e2_4 gs1e2_3 gs1e2_2 gs1e2_1 gs1e2_0 i2c-readback 18 gs2-header 77 gs2h_ 7 gs2h_ 6 gs2h_ 5 gs2h_ 4 gs2h_ 3 gs2h_ 2 gs2h_ 1 gs2h_ 0 i2c-readback 19 gs2-odd 1 78 gs2o1_ 7 gs2o1_ 6 gs2o1_ 5 gs2o1_ 4 gs2o1_ 3 gs2o1_ 2 gs2o1_ 1 gs2o1_ 0 i2c-readback 20 gs2-odd 2 79 gs2o2_ 7 gs2o2_ 6 gs2o2_ 5 gs2o2_ 4 gs2o2_ 3 gs2o2_ 2 gs2o2_ 1 gs2o2_ 0 i2c-readback 21 gs2-odd 3 7a gs2o3_ 7 gs2o3_ 6 gs2o3_ 5 gs2o3_ 4 gs2o3_ 3 gs2o3_ 2 gs2o3_ 1 gs2o3_ 0 i2c-readback 22 gs2-odd 4 7b gs2o4_ 7 gs2o4_ 6 gs2o4_ 5 gs2o4_ 4 gs2o4_ 3 gs2o4_ 2 gs2o4_ 1 gs2o4_ 0 i2c-readback 23 gs2-even 1 7c gs2e1_ 7 gs2e1_ 6 gs2e1_ 5 gs2e1_ 4 gs2e1_ 3 gs2e1_ 2 gs2e1_ 1 gs2e1_ 0 i2c-readback 24 gs2-even 2 7d gs2e2_ 7 gs2e2_ 6 gs2e2_ 5 gs2e2_ 4 gs2e2_ 3 gs2e2_ 2 gs2e2_ 1 gs2e2_ 0 i2c-readback 25 gs2-even 3 7e gs2e3_ 7 gs2e3_ 6 gs2e3_ 5 gs2e3_ 4 gs2e3_ 3 gs2e3_ 2 gs2e3_ 1 gs2e3_ 0 i2c-readback 26 gs2-even 4 7f gs2e4_ 7 gs2e4_ 6 gs2e4_ 5 gs2e4_ 4 gs2e4_3 gs2e4_ 2 gs2e4_ 1 gs2e4_ 0 registers 80 to ff used by x - port, i - port and the scaler task independent global settings 1 global control1 80 cmod 0 teb tea icks3 icks2 icks1 icks0 reserved 81 0 0 0 0 0 ftime v_eav1 v_eav0 reserved 82 0 0 0 0 0 0 0 0 x-port i/o delay and enable control 83 0 0 xpck1 xpck0 0 xrqt xpe1 xpe0 i - port signal definitions 84 idg11 idg10 idg01 idg00 idv1 idv0 idh1 idh0 i-port signal polarities 85 iswp1 iswp0 illv ig1p ig0p irvp irhp idqp i - port fifo flag control and arbitration 86 impak vitx idg12 idg02 ffl1 ffl0 fel1 fel0 i-port i/o delay and enable control 87 ipck3 ipck2 ipck1 ipck0 0 0 ipe1 ipe0 power save control 88 ch2en ch1en swrst dprog slm3 0 slm1 slm0 reserved 89 to 8e 0 0 0 0 0 0 0 0 scaler status information 8f xtri itri ffil ffov prdon err_of fidsci fidsco register function sub addr d7 d6 d5 d4 d3 d2 d1 d0
preliminary nda required con?dential - nda required page 122 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 task a definition registers 90 to bf basic settings and acquisition window definition task handling control 90 conlh ofidc fskp2 fskp1 fskp0 rptsk strc1 strc0 x - port formats and configuration 91 conlv hldfv scsrc1 scsrc0 scrqe fsc2 fsc1 fsc0 x - port input reference signal definition 92 xfdv xfdh xdv1 xdv0 xcode xdh xdq xcks i - port formats and configuration 93 icode ins80 fysk foi1 foi0 fsi2 fsi1 fsi0 horizontal input window start (1) 94 xo7 xo6 xo5 xo4 xo3 xo2 xo1 xo0 (continue) 95 0 0 0 0 xo11 xo10 xo9 xo8 horizontal input window length 96 xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 (continue) 97 0 0 0 0 xs11 xs10 xs9 xs8 vertical input window start ( 98 yo7 yo6 yo5 yo4 yo3 yo2 yo1 yo0 (continue) 99 0 0 0 0 yo11 yo10 yo9 yo8 vertical input window length 9a ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 (continue) 9b fmod 0 0 0 ys11 ys10 ys9 ys8 horizontal output window length 9c xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 (continue) 9d 0 0 0 0 xd11 xd10 xd9 xd8 vertical output window length 9e yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 (continue) 9f 0 0 0 0 yd11 yd10 yd9 yd8 fir filtering and prescaling horiz. prescaling a0 0 0 xpsc5 xpsc4 xpsc3 xpsc2 xpsc1 xpsc0 accumulation length a1 0 0 xacl5 xacl4 xacl3 xacl2 xacl1 xacl0 prescaler dc gain and fir prefilter control a2 pfuv1 pfuv0 pfy1 pfy0 xc2_1 xdcg2 xdcg1 xdcg0 reserved a3 0 0 0 0 0 0 0 0 luminance brightness a4 brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 luminance contrast a5 cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 chroma saturation a6 satn7 satn6 satn5 satn4 satn3 satn2 satn1 satn0 reserved a7 0 0 0 0 0 0 0 0 horizontal phase scaling horiz. scaling increment luma a8 xscy7 xscy6 xscy5 xscy4 xscy3 xscy2 xscy1 xscy0 register function sub addr d7 d6 d5 d4 d3 d2 d1 d0
preliminary nda required con?dential - nda required page 123 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 (continue) a9 0 0 0 xscy12 xscy11 xscy10 xscy9 xscy8 horizontal phase offset luma aa xphy7 xphy6 xphy5 xphy4 xphy3 xphy2 xphy1 xphy0 reserved ab horiz. scaling increment chroma ac xscc7 xscc6 xscc5 xscc4 xscc3 xscc2 xscc1 xscc0 (continue) ad 0 0 0 xscc12 xscc11 xscc10 xscc9 xscc8 horizontal phase offset chroma ae xphc7 xphc6 xphc5 xphc4 xphc3 xphc2 xphc1 xphc0 reserved af 0 0 0 0 0 0 0 0 vertical scaling vertical scaling increment luma b0 yscy7 yscy6 yscy5 yscy4 yscy3 yscy2 yscy1 yscy0 (b0 continued) b1 yscy15 yscy14 yscy13 yscy12 yscy11 yscy10 yscy9 yscy8 vertical scaling increment chroma b2 yscc7 yscc6 yscc5 yscc4 yscc3 yscc2 yscc1 yscc0 (b2 continued) b3 yscc15 yscc14 yscc13 yscc12 yscc11 yscc10 yscc9 yscc8 vertical scaling mode control b4 0 0 0 ymir 0 0 0 ymode reserved b5 to b7 vertical phase offset chroma 00 b8 ypc07 ypc06 ypc05 ypc04 ypc03 ypc02 ypc01 ypc00 vertical phase offset chroma 01 b9 ypc17 ypc16 ypc15 ypc14 ypc13 ypc12 ypc11 ypc10 vertical phase offset chroma 10 ba ypc27 ypc26 ypc25 ypc24 ypc23 ypc22 ypc21 ypc20 vertical phase offset chroma 11 bb ypc37 ypc36 ypc35 ypc34 ypc33 ypc32 ypc31 ypc30 vertical phase offset luma 00 bc ypy07 ypy06 ypy05 ypy04 ypy03 ypy02 ypy01 ypy00 vertical phase offset luma 01 bd ypy17 ypy16 ypy15 ypy14 ypy13 ypy12 ypy11 ypy10 vertical phase offset luma 10 be ypy27 ypy26 ypy25 ypy24 ypy23 ypy22 ypy21 ypy20 vertical phase offset luma 11 bf ypy37 ypy36 ypy35 ypy34 ypy33 ypy32 ypy31 ypy30 task b definition registers c0 to ef basic settings and acquisition window definition task handling control c0 conlh ofidc fskp2 fskp1 fskp0 rptsk strc1 strc0 x - port formats and configuration c1 conlv hldfv scsrc1 scsrc0 scrqe fsc2 fsc1 fsc0 register function sub addr d7 d6 d5 d4 d3 d2 d1 d0
preliminary nda required con?dential - nda required page 124 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 input reference signal definition control c2 xfdv xfdh xdv1 xdv0 xcode xdh xdq xcks i - port formats and configuration c3 icode ins80 fysk foi1 foi0 fsi2 fsi1 fsi0 horizontal input window start (1) c4 xo7 xo6 xo5 xo4 xo3 xo2 xo1 xo0 (continue) c5 0 0 0 0 xo11 xo10 xo9 xo8 horizontal input window length c6 xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 (continue) c7 0 0 0 0 xs11 xs10 xs9 xs8 vertical input window start ( c8 yo7 yo6 yo5 yo4 yo3 yo2 yo1 yo0 (continue) c9 0 0 0 0 yo11 yo10 yo9 yo8 vertical input window length ca ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 (continue) cb fmod 0 0 0 ys11 ys10 ys9 ys8 horizontal output window length cc xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 (continue) cd 0 0 0 0 xd11 xd10 xd9 xd8 vertical output window length ce yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 (continue) cf 0 0 0 0 yd11 yd10 yd9 yd8 fir filtering and prescaling horiz. prescaling d0 0 0 xpsc5 xpsc4 xpsc3 xpsc2 xpsc1 xpsc0 accumulation length d1 0 0 xacl5 xacl4 xacl3 xacl2 xacl1 xacl0 prescaler dc gain and fir prefilter control d2 pfuv1 pfuv0 pfy1 pfy0 xc2_1 xdcg2 xdcg1 xdcg0 reserved d3 0 0 0 0 0 0 0 0 luminance brightness d4 brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 luminance contrast d5 cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 chroma saturation d6 satn7 satn6 satn5 satn4 satn3 satn2 satn1 satn0 reserved d7 0 0 0 0 0 0 0 0 horizontal phase scaling horiz. scaling increment luma d8 xscy7 xscy6 xscy5 xscy4 xscy3 xscy2 xscy1 xscy0 (continue) d9 0 0 0 xscy12 xscy11 xscy10 xscy9 xscy8 horizontal phase offset luma da xphy7 xphy6 xphy5 xphy4 xphy3 xphy2 xphy1 xphy0 reserved db 0 0 0 0 0 0 0 0 horiz. scaling increment chroma dc xscc7 xscc6 xscc5 xscc4 xscc3 xscc2 xscc1 xscc0 register function sub addr d7 d6 d5 d4 d3 d2 d1 d0
preliminary nda required con?dential - nda required page 125 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 (continue) dd 0 0 0 xscc12 xscc11 xscc10 xscc9 xscc8 horizontal phase offset chroma de xphc7 xphc6 xphc5 xphc4 xphc3 xphc2 xphc1 xphc0 reserved df 0 0 0 0 0 0 0 0 vertical scaling vertical scaling increment luma e0 yscy7 yscy6 yscy5 yscy4 yscy3 yscy2 yscy1 yscy0 (e0 continued) e1 yscy15 yscy14 yscy13 yscy12 yscy11 yscy10 yscy9 yscy8 vertical scaling increment chroma e2 yscc7 yscc6 yscc5 yscc4 yscc3 yscc2 yscc1 yscc0 (e2 continued) e3 yscc15 yscc14 yscc13 yscc12 yscc11 yscc10 yscc9 yscc8 vertical scaling mode control e4 0 0 0 ymir 0 0 0 ymode reserved e5 to e7 0 0 0 0 0 0 0 0 vertical phase offset chroma 00 e8 ypc07 ypc06 ypc05 ypc04 ypc03 ypc02 ypc01 ypc00 vertical phase offset chroma 01 e9 ypc17 ypc16 ypc15 ypc14 ypc13 ypc12 ypc11 ypc10 vertical phase offset chroma 10 ea ypc27 ypc26 ypc25 ypc24 ypc23 ypc22 ypc21 ypc20 vertical phase offset chroma 11 eb ypc37 ypc36 ypc35 ypc34 ypc33 ypc32 ypc31 ypc30 vertical phase offset luma 00 ec ypy07 ypy06 ypy05 ypy04 ypy03 ypy02 ypy01 ypy00 vertical phase offset luma 01 ed ypy17 ypy16 ypy15 ypy14 ypy13 ypy12 ypy11 ypy10 vertical phase offset luma 10 ee ypy27 ypy26 ypy25 ypy24 ypy23 ypy22 ypy21 ypy20 vertical phase offset luma 11 ef ypy37 ypy36 ypy35 ypy34 ypy33 ypy32 ypy31 ypy30 second pll (pll2) and pulsegenerator programming lfcos per line f0 splpl7 splpl6 splpl5 splpl4 splpl4 splpl2 splpl1 splpl0 p-/i- param. select., pll m ode, pll h -src., lfcos per line f1 sppi3 sppi2 sppi1 sppi0 spmod1 spmod0 sphsel splpl8 nominal pll2 dto increment f2 spninc 7 spninc 6 spninc 5 spninc 4 spninc 3 spninc 2 spninc 1 spninc 0 f3 spninc 15 spninc 14 spninc 13 spninc 12 spninc 11 spninc 10 spninc 9 spninc 8 pll2 status f4 0 0 0 0 0 0 0 splock pulsgen. line length f5 pglen7 pglen6 pglen5 pglen4 pglen3 pglen2 pglen1 pglen0 pulse a position, pulsgen resync. pulsgen. h-src., pulsgen. line length f6 pghaps3 pghaps2 pghaps1 pghaps0 0 pgres pghsel pglen8 pulse a position f7 pghaps11 pghaps10 pghaps9 pghaps8 pghaps7 pghaps6 pghaps5 pghaps4 register function sub addr d7 d6 d5 d4 d3 d2 d1 d0
preliminary nda required con?dential - nda required page 126 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 pulse b position f8 pghbps3 pghbps2 pghbps1 pghbps0 0 0 0 0 pulse b position f9 pghbps11 pghbps10 pghbps9 pghbps8 pghbps7 pghbps6 pghbps5 pghbps4 pulse c position fa pghcps3 pghcps2 pghcps1 pghcps0 0 0 0 0 pulse c position fb pghcps11 pghcps10 pghcps9 pghcps8 pghcps7 pghcps6 pghcps5 pghcps4 reserved fc 0 0 0 0 0 0 0 0 reserved fd 0 0 0 0 0 0 0 0 reserved fe 0 0 0 0 0 0 0 0 s_pll max. phase error threshold, pll2 no. of lines threshold ff spthrl3 spthrl2 spthrl1 spthrl0 spthrm3 spthrm2 spthrm1 spthrm0 register function sub addr d7 d6 d5 d4 d3 d2 d1 d0
preliminary nda required con?dential - nda required page 127 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16 detailed description of the control registers 16.1 chip version / ident register 16.1.1 c hip v ersion table 49 chip version (sa00), read only register 16.1.2 c hip id table 50 chip id (sa00) function (1) 1. this register contains the current version identification number of the chip. initial version: 0001. logic levels id07 id06 id05 id04 chip version (cv) cv3 cv2 cv1 cv0 function (1) 1. this register can be evaluated by alternating write/read cycles write (hex) read back (hex) id3 to id0 chip id 00 1 01 f 02 7 03 1 04 1 05 5 06 d 07 0 08 e 09 version 0a .. of 0
preliminary nda required con?dential - nda required page 128 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2 programming register decoder 16.2.1 s ubaddress 01 a nalog i nput c ontrol 0, i ncrement d elay table 51 horizontal increment delay (sa 01) table 52 analog control 0 (sa01) function (1) 1. the programming of the horizontal increment delay is used to match internal processing delays to the delay of the ad-converter. use recommended position only. idel3 idel2 idel1 idel0 no update 1 1 1 1 min. delay 1 1 1 0 recommended position 1000 max delay 0 0 0 0 function logic levels update hysteresis for 9-bit gain, see figure 8 on page 26 control bits d5 and d4 gudl 1 gudl 0 off 00 1 lsb 0 1 2 lsb 1 0 3 lsb 1 1 white peak control off control bit d6 wpoff white peak control active (ad-signal is attenuated, if nominal luminance output white level is exceeded) 0 white peak control disabled 1
preliminary nda required con?dential - nda required page 129 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.2 s ubaddress 02 a nalog i nput c ontrol 1 table 53 analog control 1 (sa 02) note: to take full advantage of the yc-modes 6 to 9 the i 2 c-bit byps (sub address 09h, bit 7) must be set to 1 (full luminance bandwidth) function logic levels analog control 1 (mode select, see table 54 on page 130) (1) 1. in order to reduce power consumption of the device use the registers ch1en and ch2en (subaddress 88h, bits 7 and 6) to switch of either of the adcs not used in cvbs modes. control bits d3 to d0 mode3 mode2 mode1 mode0 mode 0: cvbs (automatic gain) from ai11 (pin 20) 0000 mode 1: cvbs (automatic gain) from ai12 (pin 18) 0001 mode 2: cvbs (automatic gain) from ai21 (pin 16) 0010 mode 3: cvbs (automatic gain) from ai22 (pin 14) 0011 mode 4: cvbs (automatic gain) from ai23 (pin 12) 0100 mode 5: cvbs (automatic gain) from ai24 (pin 10) 0101 mode 6: y (automatic gain) from ai11 (pin 20) + c (gain adjusted via gai2[8:0]) from ai21 (pin 16) 0110 mode 7: y (automatic gain) from ai12 (pin 18) + c (gain adjusted via gai2[8:0]) from ai22 (pin 14) 0111 mode 8: y (automatic gain) from ai11 (pin 20) + c (gain channel 2 adapted to y gain) from ai21 (pin 16) 1000 mode 9: y (automatic gain) from ai12 (pin 18) + c (gain channel 2 adapted to y gain) from ai22 (pin 14) 1001 mode 10 to 15: reserved 1 0 1 1 ... ... ... 1111 analog function select fuse, see figure 7 on page 25 control bits d7 and d6 fuse 1 fuse 0 ampli?er plus anti-alias ?lter bypassed 00 01 ampli?er active 1 0 ampli?er plus anti-alias ?lter active 1 1
preliminary nda required con?dential - nda required page 130 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 mode 0 cvbs (automatic gain) mode 1 cvbs (automatic gain) mode 2 cvbs (automatic gain) mode 3 cvbs (automatic gain) mode 4 cvbs (automatic gain) mode 5 cvbs (automatic gain) mode 6 y+c (gain channel 2 adjusted via gai2) mode 7 y+c (gain channel 2 adjusted via gai2) table 54 effects of mode[3:0] settings ai23 ai22 ai12 ai11 chroma luma ad2 ad1 ai21 ai24 ai23 ai22 ai12 ai11 chroma luma ad2 ad1 ai21 ai24 ai22 ai21 ai12 ai11 chroma luma ad2 ad1 ai21 ai24 ai23 ai22 ai12 ai11 chroma luma ad2 ad1 ai21 ai24 ai23 ai22 ai12 ai11 chroma luma ad2 ad1 ai21 ai24 ai23 ai22 ai12 ai11 chroma luma ad2 ad1 ai21 ai24 ai23 ai22 ai12 ai11 chroma luma ad2 ad1 ai21 ai24 ai23 ai22 ai12 ai11 chroma luma ad2 ad1 ai21 ai24
preliminary nda required con?dential - nda required page 131 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 note: to take full advantage of the yc-modes 6 to 9 the control-bit byps (sub address 09h, bit 7) should be set to 1 (full luminance bandwidth) mode 8 y+c (gain channel 2 adapted to y-gain) mode 9 y+c (gain channel 2 adapted to y-gain) table 54 effects of mode[3:0] settings ai23 ai22 ai12 ai11 chroma luma ad2 ad1 ai21 ai24 ai23 ai22 ai12 ai11 chroma luma ad2 ad1 ai21 ai24
preliminary nda required con?dential - nda required page 132 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.3 s ubaddress 03 a nalog i nput c ontrol 2 table 55 analog control 2 (aico2) (sa03) function logic level data bit static gain control channel 1 (gai18) (see sa04) sign bit of gain control see table 56 d0 static gain control channel 2 (gai28) (see sa05) sign bit of gain control see table 57 d1 gain control ?x (gafix) automatic gain controlled by mode[3:0] 0 d2 gain is user programmable via gai1 + gai2 1 automatic gain control integration (holdg) agc active 0 d3 agc integration hold (frozen) 1 color peak off (cpoff) color peak control active (ad-signal is attenuated, if maximum input level is exceeded, avoids clipping effects on screen) 0 d4 color peak off 1 agc hold during vertical blanking period (vbsl) short vertical blanking (agc disabled during equalization- and serration pulses) 0 d5 long vertical blanking (agc disabled from start of pre equalization pulses until start of active video (line 22 for 60 hz, line 24 for 50 hz) 1 hl not reference select (hlnrs) normal clamping if decoder is in unlocked state 0 d6 reference select if decoder is in unlocked state 1
preliminary nda required con?dential - nda required page 133 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.4 s ubaddress 04 a nalog i nput c ontrol 3 table 56 gain control analog (aic03); static gain control channel 1 gai1 (sa 03, sa 04) 16.2.5 s ubaddress 05 a nalog i nput c ontrol 4 table 57 gain control analog (aic04); static gain control channel 2 gai2 (sa 03, sa 05) 16.2.6 s ubaddress 06 h orizontal s ync s ta rt table 58 horizontal sync begin (sa 06) decimal value gain (db) sign bit 03h d0 control bits 04h d7 to 04h d0 gai18 gai17 gai16 gai15 gai14 gai13 gai12 gai11 gai10 0.... - 3.00 00000000 ....144 0 0 1 0 0 1 0 0 0 0 145.... 0 0 1 0 0 1 0 0 0 1 ....511 +6.0 1 1 1 1 1 1 1 1 1 decimal value gain (db) sign bit 03h d1 control bits 05h d7 to 05h d0 gai28 gai27 gai26 gai25 gai24 gai23 gai22 gai21 gai20 0.... -3.0 0 00000000 ....144 0 0 10010000 145.... 0 0 10010001 ....511 +6.0 1 11111111 delay time (step size = 8/llc) control bits d7 to d0 hsb7 hsb6 hsb5 hsb4 hsb3 hsb2 hsb1 hsb0 -128...-109 (50hz) -128...-108 (60hz) forbidden (outside available central counter range) -108 (50hz) ... -107 (60hz) ... 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 ...108 (50hz) ...107 (60hz) 0 0 1 1 1 1 0 0 1 1 1 0 0 1 0 1 109...127 (50hz) 108...127 (60hz) forbidden (outside available central counter range)
preliminary nda required con?dential - nda required page 134 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.7 s ubaddress 07 h orizontal s ync s top table 59 horizontal sync stop (sa 07) delay time (step size = 8/llc) control bits d7 to d0 hss7 hss6 hss5 hss4 hss3 hss2 hss1 hss0 -128...-109 (50hz) -128...-108 (60hz) forbidden (outside available central counter range) -108 (50hz) ... -107 (60hz) ... 1 1 0 0 0 0 1 1 0 0 1 1 0 0 0 1 ...108 (50hz) ...107 (60hz) 0 0 1 1 1 1 0 0 1 1 1 0 0 1 0 1 109...127 (50hz) 108...127 (60hz) forbidden (outside available central counter range)
preliminary nda required con?dential - nda required page 135 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.8 s ubaddress 08 s ync c ontrol table 60 sync control (sa 08) function control bits logic levels data bits vertical noise reduction (vnoi) normal mode ( recommended setting ) vnoi1 0 d1 vnoi0 0 d0 fast mode (applicable for stable sources only, automatic ?eld detection [aufd] must be disabled) vnoi1 0 d1 vnoi0 1 d0 free running mode vnoi1 1 d1 vnoi0 0 d0 vertical noise reduction bypassed vnoi1 1 d1 vnoi0 1 d0 horizontal pll (hpll) pll closed hpll 0 d2 pll open, horizontal frequency ?xed hpll 1 horizontal time constant selection (htc1, htc0) tv mode (recommended for poor quality tv signals only, do not use for new applications) htc1, htc0 00 d4,d3 vtr mode (recommended if a de?ection control circuit is directly connected at the output of the decoder) 01 automatic tv/vrc detection (recommended setting) threshold is programmable via atvt[1:0], see sa 1b 10 fast locking mode 11 forced odd/even toggle foet odd/even-signal toggles only with interlaced source foet 0 d5 odd/even-signal toggles ?eld wise even if source is non-interlaced 1 field selection (fsel, active, if aufd = 1) 50 hz, 625 lines fsel 0 d6 60 hz, 525 lines 1 automatic ?eld detection (aufd) field state directly controlled via fsel aufd 0 d7 automatic ?eld detection ( recommended setting )1
preliminary nda required con?dential - nda required page 136 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.9 s ubaddress 09 l uminance control table 61 luminance control (sa 09) function bits logic levels data bits sharpness control, luminance ?lter characteristic (lufi), see figure 17 on page 37 resolution enhancement ?lter 8.0 db at 4.1 mhz lufi[3:0] 0001 d3 .. d0 resolution enhancement ?lter 6.8 db at 4.1 mhz lufi[3:0] 0010 resolution enhancement ?lter 5.1 db at 4.1 mhz lufi[3:0] 0011 resolution enhancement ?lter 4.1 db at 4.1 mhz lufi[3:0] 0100 resolution enhancement ?lter 3.0 db at 4.1 mhz lufi[3:0] 0101 resolution enhancement ?lter 2.3 db at 4.1 mhz lufi[3:0] 0110 resolution enhancement ?lter 1.6 db at 4.1 mhz lufi[3:0] 0111 plain lufi[3:0] 0000 low pass ?lter 2 db at 4.1 mhz lufi[3:0] 1000 low pass ?lter 3 db at 4.1 mhz lufi[3:0] 1001 low pass ?lter 3 db at 3.3 mhz, 4 db at 4.1 mhz lufi[3:0] 1010 low pass ?lter 3 db at 2.6 mhz, 8 db at 4.1 mhz lufi[3:0] 1011 low pass ?lter 3 db at 2.4 mhz, 14 db at 4.1 mhz lufi[3:0] 1100 low pass ?lter 3 db at 2.2 mhz, notch at 3.4 mhz lufi[3:0] 1101 low pass ?lter 3 db at 1.9 mhz, notch at 3.0 mhz lufi[3:0] 1110 low pass ?lter 3 db at 1.7 mhz, notch at 2.5 mhz lufi[3:0] 1111 remodulation bandwidth for luminance (lubw), see ?gures 13 to 16 small remodulation bandwidth (narrow chroma notch => higher luminance bandwidth) lubw 0 d4 large remodulation bandwidth (wider chroma notch => smaller luminance bandwidth) lubw 1 processing delay in non comb?lter mode (ldel) processing delay is equal to internal pipelining delay (recommended setting) ldel 0 d5 one (ntsc-standards) or two (pal-standards) video lines additional processing delay ldel 1 adaptive luminance comb ?lter (ycomb) disabled (= chrominance trap enabled, if byps = 0) ycomb 0 d6 active, if byps = 0 ycomb 1 chrominance trap / comb ?lter bypass (byps) chrominance trap or luminance comb ?lter active, default for cvbs mode byps 0 d7 chrominance trap or luminance comb ?lter bypassed; default for s-video mode byps 1
preliminary nda required con?dential - nda required page 137 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.10 s ubaddress 0a d ecoder b rightness table 62 luminance brightness control decoder part dbri7 to dbri0 (sa 0a) 16.2.11 s ubaddress 0b d ecoder c ontrast table 63 luminance contrast control decoder part dcon7 to dcon0 (sa 0b) 16.2.12 s ubaddress 0c d ecoder s aturation table 64 chrominance saturation control decoder part dsat7 to dsat0 (sa 0c) offset control bits d7 to d0 dbri7 dbri6 dbri5 dbri4 dbri3 dbri2 dbri1 dbri0 255 (bright) 1 1 1 1 1 1 1 1 128 (itu level) 1 0 0 0 0 0 0 0 0 (dark) 0 0 0 0 0 0 0 0 gain control bits d7 to d0 dcon7 dcon6 dcon5 dcon4 dcon3 dcon2 dcon1 dcon0 1.984 (maximum) 0 1 1 1 1 1 1 1 1.063 (itu level) 0 1 0 0 0 1 0 0 1.0 01000000 0 (luminance off) 0 0 0 0 0 0 0 0 - 1.0 (inverse luminance) 1 1 0 0 0 0 0 0 - 2.0 (inverse luminance) 1 0 0 0 0 0 0 0 gain control bits d7 to d0 dsat7 dsat6 dsat5 dsat4 dsat3 dsat2 dsat1 dsat0 1.984 (maximum) 0 1 1 1 1 1 1 1 1.0 (itu level) 0 1 0 0 0 0 0 0 0 (colour off) 0 0 0 0 0 0 0 0 - 1.0 (inverse chrominance) 1 1 0 0 0 0 0 0 - 2.0 (inverse chrominance) 1 0 0 0 0 0 0 0
preliminary nda required con?dential - nda required page 138 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.13 s ubaddress 0d c hrominance h ue table 65 chrominance hue control huec7 to huec0 (sa 0d) hue phase (deg) control bits d7 to d0 huec7 huec6 huec5 huec4 huec3 huec2 huec1 huec0 +178.6.... 0 1 1 1 1 1 1 1 ....0.... 0 0 0 0 0 0 0 0 .... - 180.0 1 0 0 0 0 0 0 0
preliminary nda required con?dential - nda required page 139 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.14 s ubaddress 0e c hrominance c ontrol 1 table 66 chrominance control 1 (sa 0e) function name logic levels data bits adaptive chrominance comb ?lter (ccomb) disabled ccomb 0 d0 active 1
preliminary nda required con?dential - nda required page 140 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 automatic chrominance standard detection control 0 (auto0) note: automatic chrominance standard detection control 1 (auto1) is located at subaddress 14h, d2 the automatic standard detection circuit does not only search and lock to any broadcast standard, but provides also some default settings dependent on the chosen automatic level. e.g it automatically disables the comb?lter or remodulation functionality if y/c-mode is selected or a b&w source is present. also the bandwidths of the internal ?lters are adapted to the detected standard. however, if these setting are not convenient for the customers application, lower auto levels can be chosen, so that only the standard search and lock is active and all other settings can be programmed independently. disabled auto[1:0] 00 sa14:d2, sa0e: d1 auto mode active (highest level), ?lter settings and sharpness control are preset to default values according to the detected standard and mode ( recommended position ) the following registers are automatically set dependent on the following conditions: 01 mode dcvf lcbw lubw ycomb ccomb lufi chbw pa l comb 0 110 0 p p 0000 0 pa l nocomb 0 000 0 p p 0110 0 pal y/c 0 110 0 0 0 0000 1 ntsc comb 1 110 0 p p 0000 0 ntsc nocomb 0 000 0 p p 0110 0 ntsc y/c 1 110 0 0 0 0000 1 secam x 000 1 0 x 1011 0 secam y/c x 000 x 0 x 0000 0 b & w x xxx x 0 x 0000 x p: programming is required and valid x: setting has no in?uence y/c-mode has to be selected via byps = 1 auto mode active (medium level), ?lter settings are preset to default values according to the detected standard and mode like auto[1:0] = 01, with the following differences: sharpness control (lufi[3:0]) is freely programmable ccomb is freely programmable chbw is freely programmable 10 auto mode active (lowest level), automatic standard recognition, but no ?lter presets 11 function name logic levels data bits
preliminary nda required con?dential - nda required page 141 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 fast colour time constant (fctc) nominal time constant fctc 0 d2 fast time constant for special applications (high quality input source, fast chroma lock required, automatic standard detection off 1 disable chrominance vertical ?lter and pal phase error correction (dcvf) chrominance vertical ?lter, pal phase error correction on (during active video lines) dcvf 0 d3 chrominance vertical ?lter, pal phase error correction permanently off 1 colour standard selection in non auto-mode (cstd0 to cstd2); logic levels 110 and 111 are reserved, do not use 50 hz / 625 lines 60 hz / 525 lines logic levels data bits pal bgdhi (4.43mhz) ntsc m (3.58mhz) cstd[2:0] 000 d6 to d4 ntsc 4.43 (50 hz) pal 4.43 (60 hz) 001 combination-pal n (3.58mhz) ntsc 4.43 (60 hz) 010 ntsc n (3.58mhz) pal m (3.58mhz) 011 reserved ntsc-japan (3.58mhz) 100 secam reserved 101 reserved reserved 110 reserved reserved 111 colour standard selection (cstd0 to cstd2) in auto mode (auto mode is selected if either auto0 or auto1 is set, see above) 50 hz / 625 lines 60 hz / 525 lines logic levels data bits preferred standard is pal bgdhi (4.43mhz) preferred standard is ntsc m (3.58mhz) cstd[2:0] 000 d6 to d4 reserved reserved 001 reserved reserved 010 reserved reserved 011 preferred standard is pal bgdhi (4.43mhz) preferred standard is ntsc-japan (3.58mhz, no 7.5 ire-offset) 100 preferred standard is secam preferred standard is ntsc m (3.58mhz) 101 reserved reserved 110 reserved reserved 111 note: the meaning of preferred standard is, that the internal search machine will always give priority to the selected standard, thus the recognition time for these standards is kept short. function name logic levels data bits
preliminary nda required con?dential - nda required page 142 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 clear dto (cdto) disabled cdto 0 d7 every time cdto is set, the internal subcarrier dto phase is reset to 0 and the rtco output generates a logic 0 at time slot 68. so an identical subcarrier phase can be generated by an external device (e.g. an encoder). the dto-reset takes also care that the internal remodulation carriers phase aligned to the internal demodulation phase. a dto-reset must be initiated after reprogramming the color standard cstd in non auto mode. however, if automatic standard searching mode is activated via auto[1:0] <> 00 an internal dto-reset is generated after change of standard. that means it is only necessary to generate a dto reset after connection to an external encoder. 1 function name logic levels data bits
preliminary nda required con?dential - nda required page 143 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.15 s ubaddress 0f c hrominance g ain c ontrol table 67 chrominance gain control (sa 0f) function logic levels chroma gain value (if acgc is set to 1) control bits d6 to d0 cgain6 cgain5 cgain4 cgain3 cgain2 cgain1 cgain0 minimum gain (0.5) 0 0 0 0 0 0 0 nominal gain (1.125) 0 1 0 0 1 0 0 maximum gain (7.5) 1 1 1 1 1 1 1 automatic chroma gain control acgc control bit d7 on (recommended setting) 0 programmable gain via cgain[6:0], 1
preliminary nda required con?dential - nda required page 144 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.16 s ubaddress 10 c hrominance /l uminance c ontrol 2 table 68 chrominance/luminance control 2 (sa 10) function logic levels combined luminance/chrominance bandwidth adjustment (see figures 11 to 16 ) control bits d2 to d0 lcbw2 lcbw1 lcbw0 smallest chrominance bandwidth / largest luminance bandwidth 000 recommended setting for non comb?lter mode (ycomb=0,ccomb=0) 001 recommended setting for active adaptive comb?lter (ycomb=1,ccomb=1) 110 largest chrominance bandwidth / smallest luminance bandwidth 111 chrominance bandwidth (see ?gures 11 and 12 ) control bit d3 chbw small 0 wide 1 fine offset adjustment r-y component control bits d5 and d4 offv1 offv0 0 lsb 0 0 +1/4 lsb 0 1 +1/2 lsb 1 0 +3/4 lsb 1 1 fine offset adjustment b-y component control bits d7 and d6 offu1 offu0 0 lsb 0 0 +1/4 lsb 0 1 +1/2 lsb 1 0 +3/4 lsb 1 1
preliminary nda required con?dential - nda required page 145 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.17 s ubaddress 11 m ode /d elay c ontrol table 69 mode / delay control sa 11 function logic levels luminance delay compensation (steps in 2/llc) control bits d2 to d0 ydel2 ydel1 ydel0 - 4... 1 0 0 ...0... (recommended) 000 ...3 0 1 1 output polarity rts0 control bit d4 rtp0 rts0 non inverted 0 rts0 inverted 1 fine position of hs-pulse, available on outputs rtso, rts1 and xdh, step size of 2/llc control bits d5 and d4 hdel1 hdel0 000 101 210 311 output polarity rts1 control bit d6 rtp1 rts1 non inverted 0 rts1 inverted 1 colour on control bit d7 colo automatic colour killer enabled ( recommended setting )0 colour forced on 1
preliminary nda required con?dential - nda required page 146 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.18 s ubaddress 12 rts0/1 o utput c ontrol table 70 rts0 output control (sa 12) note 1. the polarity of any signal on rts0 can be inverted via rtp0 (sub address 11 bit 3). function logic levels rts0 output control (1) d3 to d0 rtse03 rtse02 rtse01 rtse00 tristate 0000 constant low 0001 cref (13.5 mhz toggling pulse, see figure 24 on page 48) 0010 cref2 (6.75 mhz toggling pulse, see figure 24 on page 48) 0011 hl (horizontal lock indicator), selectable via hlsel (sub addr. 11h, bit 4): hlsel = 0: standard horizontal lock indicator hlsel =1: fast horizontal lock indicator (use is not recommended for sources with unstable timebase e. g. vcrs) 0: unlocked 1: locked 0100 vl (vertical & horizontal lock) 0: unlocked 1: locked 0101 dl (vertical & horizontal lock & color detected) 0: unlocked 1: locked 0110 reserved 0111 href horizontal reference signal: indicates 720 pixels valid data on the expansion port. the positive slope marks the beginning of a new active line. href is also generated during the vertical blanking interval, see figure 24 on page 48 1000 hs, programmable width in llc8 steps via hsb[7:0] and hss[7:0] (sub addr. 06h and 07h), ?ne position adjustment in llc2 steps via hdel[1:0] (sub addr. 11h, bits 5:4), see figure 24 on page 48) 1001 hq (href gated with vgate) 1010 reserved 1011 v123 (vertical sync, see figure 22 on page 46 and figure 23 on page 47) 1100 vgate (programmable via vsta[8:0], vsto[8:0] and vgps, sub addresses 15h, 16h, and 17h) 1101 reserved 1110 fid (position programmable via vsta[8:0], sub addresses 15h and 17h, see figure 22 on page 46 and figure 23 on page 47) 1111
preliminary nda required con?dential - nda required page 147 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 71 rts1 output control (sa 12) note 1. the polarity of any signal on rts1 can be inverted via rtp1 (sub address 11 bit 6). function logic levels rts1 output control (1) d7 to d4 rtse13 rtse12 rtse11 rtse10 tristate 0000 constant low 0001 cref (13.5 mhz toggling pulse, see figure 24 on page 48) 0010 cref2 (6.75 mhz toggling pulse, see figure 24 on page 48) 0011 hl (horizontal lock indicator), selectable via hlsel (sub addr. 11h, bit 4): hlsel = 0: standard horizontal lock indicator hlsel =1: fast horizontal lock indicator (use is not recommended for sources with unstable timebase e. g. vcrs) 0: unlocked 1: locked 0100 vl (vertical & horizontal lock) 0: unlocked 1: locked 0101 dl (vertical & horizontal lock & color detected) 0: unlocked 1: locked 0110 reserved 0111 href horizontal reference signal: indicates 720 pixels valid data on the expansion port. the positive slope marks the beginning of a new active line. href is also generated during the vertical blanking interval, see figure 24 on page 48 1000 hs, programmable width in llc8 steps via hsb[7:0] and hss[7:0] (sub addr. 06h and 07h), ?ne position adjustment in llc2 steps via hdel[1:0] (sub addr. 11h, bits 5:4), see figure 24 on page 48) 1001 hq (href gated with vgate) 1010 reserved 1011 v123 (vertical sync, see figure 22 on page 46 and figure 23 on page 47) 1100 vgate (programmable via vsta[8:0], vsto[8:0] and vgps, sub addresses 15h, 16h, and 17h) 1101 reserved 1110 fid (position programmable via vsta[8:0], sub addresses 15h and 17h, see figure 22 on page 46 and figure 23 on page 47) 1111
preliminary nda required con?dential - nda required page 148 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.19 s ubaddress 13 and 1brt/x- port o utput c ontrol table 72 rt / x-port output control (sa 13, sa 1b) function logic levels xpd[7:0] - port output format selection, see also chapter 9.4 x-port output 1bh d4 13h d2 to d0 xpd[7:0] xrh xrv xdq ofts3 ofts2 ofts1 ofts0 itu656 - 8 bit standard mode y, c b ,c r [7:0] horizontal sync. signal controlled by xrhs vertical sync. signal controlled by xrvs[1:0] href && vgate 0000 modi?ed itu656-8-bit mode: standard v?ag is replaced by vgate, programmable via vsta,vsto 0001 8-bit multiplexed y,cb,cr-mode, itu- codes and 10/80 blanking values are disabled 0010 reserved reserved 0011 reserved 0100 reserved 0101 adc1-bypass-mode (msbs only) ad1[8:1] 0110 adc2-bypass-mode (msbs only) ad2[8:1] 0111 itu656-10-bit standard mode y, c b ,c r [9:2] y, c b ,c r [1] y, c b ,c r [0] 1000 modi?ed itu656-10-bit mode: standard v?ag is replaced by vgate, programmable via vsta,vsto 1001 10-bit multiplexed y,cb,cr-mode, itu- codes and 10/80 blanking values are disabled 1010 reserved reserved reserved reserved 1011 reserved 1100 reserved 1101 adc1-bypass-mode (9 bits) ad1[8:1] ad1[0] 1 1 1 0 adc2-bypass-mode (9 bits) ad2[8:1] ad2[0] 1 1 1 1
preliminary nda required con?dential - nda required page 149 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 73 rt / x-port output control sa 13 16.2.20 s ubaddress 14 a nalog /adc/a uto /c ompatibility c ontrol table 74 analog / adc / compatibility control sa 14 function logic levels horizontal lock indicator selection hlsel control bits d3 hlsel copy of inverted hlock status bit (default) 0 fast horizontal lock indicator (for special applications only) 1 x - port xrv output selection xrvs control bits d5 and d4 xrvs1 xrvs0 v123 (see figure 22 on page 46 and figure 23 on page 47 ) 00 itu656 related ?eld id (see figure 22 on page 46 and figure 23 on page 47 ) 01 inverted v123 10 inverted itu656 related ?eld id 11 x - port xrh output selection xrhs control bits d6 href, see figure 24 on page 48 0 hs (programmable: width in llc8-steps via hsb[7:0] and hss[7:0] ?ne position in llc2 steps via hdel[1:0]), see figure 24 on page 48 1 rtco output enable rtce control bits d7 tristate 0 enabled 1 function logic levels adc sample clock phase delay control bits d1 and d0 apck1 apck0 application dependent 00 01 10 11
preliminary nda required con?dential - nda required page 150 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 automatic chrominance standard detection control 1 (auto1), see explanation at subaddress 0eh control bit d2 xtout output enable (xtoute) control bit d3 pin 4 (xtout) tristated 0 pin 4 (xtout) enabled 1 analog test select (aosl) control bits 01h d7 and 14h d5, d4 aosl2 01h d7 aosl1 14h d5 aosl0 14h d4 aout connected to ground (recommended) 000 aout connected to input ch1 video 001 aout connected to input ch2 video 010 aout connected to input bpfout (llc) 011 aout connected to input bpfout2 100 reserved (gnd) 101 reserved (gnd) 110 reserved (gnd) 111 update time interval for agc-value (uptcv) control bit d6 horizontal update (once per line) 0 vertical update (once per ?eld) 1 compatibility switch for saa7199 (cm99) control bit d7 off (default) 0 on (to be set only if saa7199 is used for re-encoding in conjunction with rtco active 1 function logic levels
preliminary nda required con?dential - nda required page 151 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.21 s ubaddress 15, 17vgate s ta rt table 75 start of vgate-pulse (01-transition) and polarity change of fid-pulse, vgps = 0, see ?gures 22 and 23 (sa 15, sa 17) 16.2.22 s ubaddress 16, 17 vgate s top table 76 stop of vgate-pulse (10-transition), vgps = 0, see ?gures 22 and 23 (sa 16, sa 17) field frame line counting decimal value 17h d0 control bits 15h d7 to 15h d0 vsta8 vsta7 vsta6 vsta5 vsta4 vsta3 vsta2 vsta1 vsta0 50 hz 1st 1 312 1 00111000 2nd 314 1st 2 0.... 0 0 0 0 0 0 0 0 0 2nd 315 1st 312 ....310 1 0 0 1 1 0 1 1 1 2nd 625 60 hz 1st 4 262 1 00000110 2nd 267 1st 5 0.... 0 0 0 0 0 0 0 0 0 2nd 268 1st 265 ....260 1 0 0 0 0 0 1 0 1 2nd 3 field frame line counting decimal value 17h d0 control bits 16h d7 to 16h d0 vsto8 vsto7 vsto6 vsto5 vsto4 vsto3 vsto2 vsto1 vsto0 50 hz 1st 1 312 1 00111000 2nd 314 1st 2 0.... 0 00000000 2nd 315 1st 312 ....310 1 00110111 2nd 625 60 hz 1st 4 262 1 00000110 2nd 267 1st 5 0.... 0 00000000 2nd 268 1st 265 ....260 1 00000101 2nd 3
preliminary nda required con?dential - nda required page 152 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.23 s ubaddress 17 m isc ./vgate-msb s table 77 misc./vgate-msbs (sa 17) function logic levels control bits vsta8, see sa 15 msb vgate start see table 76 d0 vsto8, see sa 16 msb vgate stop see table 76 d1 alternative vgate position (vgps) vgate position according to tables and 76 0 d2 vgate occurs one line earlier during ?eld 2 1 standard detection search loop latency (laty) reserved 000 d5 to d3 one ?eld 001 ... ... three ?elds ( recommended value ) 011 ... ... seven ?elds 111 llc (pin 48) output enable (llc2e) enabled 0 d6 tristate 1 llc (pin 46) output enable (llce) enabled 0 d7 tristate 1
preliminary nda required con?dential - nda required page 153 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.24 s ubaddress 18 r aw data g ain c ontrol table 78 raw data gain control rawg7 to rawg0 (sa 18) 16.2.25 s ubaddress 19 r aw data o ffset c ontrol table 79 raw data offset control rawo7 to rawo0 (sa 19) gain control bits d7 to d0 rawg7 rawg6 rawg5 rawg4 rawg3 rawg2 rawg1 rawg0 255 (double ampl.) 0 1 1 1 1 1 1 1 128 (nominal level) 0 1 0 0 0 0 0 0 0 (off) 0 0 0 0 0 0 0 0 offset control bits d7 to d0 rawo7 rawo6 rawo5 rawo4 rawo3 rawo2 rawo1 rawo0 - 128 lsb 0 0 0 0 0 0 0 0 0 lsb 10000000 +128 lsb 1 1 1 1 1 1 1 1
preliminary nda required con?dential - nda required page 154 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.26 s ubaddress 1a c olor k iller l evel c ontrol table 80 secam color killer level control (sa 1a) table 81 pal/ntsc color killer level control (sa 1a) 16.2.27 s ubaddress 1b m isc .c hroma c ontrol table 82 automatic vcr/tv-detection threshold (sa 1b) table 83 automatic color limiter (sa 1b) secam color killer level control bits d3 to d0 sthr3 sthr2 sthr1 sthr0 minimum level: color is switched on at low subcarrier levels 0 0 0 0 recommended value 0 1 1 1 maximum 1 1 1 1 pal/ntsc color killer level control bits d7 to d4 qthr3 qthr2 qthr1 qthr0 minimum: color is switched on at low subcarrier levels 0 0 0 0 recommended value 0 1 1 1 maximum 1 1 1 1 automatic vcr/tv-detection threshold d7,d6 atvt[1:0] very sensitive to phase errors => early switching to fast horizontal time constant 00 recommended value 01 less sensitive to phase errors 10 insensitive to phase errors => late switching to fast horizontal time constant 11 automatic color limiter d1 acol disabled 0 active: reduces oversaturated color in case of nonstandard burst/picture_content relation (recommended) 1
preliminary nda required con?dential - nda required page 155 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 84 fast sequence correction (sa 1b) 16.2.28 s ubaddress 1c e nhanced c ombfilter c ontrol 1 table 85 horizontal difference gain (sa 1c) table 86 vertical difference gain (sa 1c) table 87 median filter gain (sa 1c) fast pal/secam sequence correction d0 fsqc sequence correction enabled once per ?eld (recommended) 0 to be used, if immediate (linewise) sequence correction is required 1 horizontal difference gain d7,d6 hodg[1:0] lowest luminance bandwidth at horizontal transients 00 higher luminance bandwidth at horizontal transients 01 recommended value 10 highest luminance bandwidth at horizontal transients 11 vertical difference gain d5,d4 vedg[1:0] highest luminance bandwidth at vertical transients 00 lower luminance bandwidth at vertical transients 01 recommended value 10 lowest luminance bandwidth at vertical transients 11 median filter gain d3,d2 medg[1:0] highest luminance bandwidth at high color saturation 00 lower luminance bandwidth at high color saturation 01 recommended value 10 lowest luminance bandwidth at high color saturation 11
preliminary nda required con?dential - nda required page 156 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 88 comb?lter threshold (sa 1c) 16.2.29 s ubaddress 1d e nhanced c ombfilter c ontrol 2 table 89 vertical difference threshold (sa 1c) comb threshold d1,d0 cmbt[1:0] lowest comb strength for signals containing small chrominance content 00 recommended value 01 higher comb strength for signals containing small chrominance content 10 highest comb strength for signals containing small chrominance content 11 vertical difference threshold d1,d0 vedt[1:0] highest comb strength for signals containing large vertical chrominance differences 00 recommended value 01 lower comb strength for signals containing large vertical chrominance differences 10 lowest comb strength for signals containing large vertical chrominance differences 11
preliminary nda required con?dential - nda required page 157 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.2.30 s ubaddresses 1e, 1f s tatus b ytes v ideo d ecoder ( read - only register ) table 90 status byte 1 video decoder (sa 1e) table 91 status byte 2 video decoder (sa 1f) i 2 c-bus control bits function data bit dcstd[1:0] detected color standard: 00: no color [bw] 01: ntsc 10: pal 11: secam d1, d0 wipa white peak loop is activated; active high d2 glimb gain value for active luminance channel is limited [min (bottom)]; active high d3 glimt gain value for active luminance channel is limited [max (top)]; active high d4 sltca slow time constant active in wipa-mode; active high d5 hlck status bit for locked horizontal frequency; low = locked, high = unlocked d6 nfld status bit for ?eld length; low = nonstandard ?eld length, high = standard ?eld length d7 i 2 c-bus control bits function data bit rdcap ready for capture (all internal loops locked); active high d0 copro copy protected source detected according to macrovision version up to 7.01 d1 colstr macrovision encoded colorstripe burst detected (any type) d2 type3 macrovision encoded colorstripe burst type 3 (4 line version) detected d3 sttb status bit for timebase of input signal; low = nonstable timebase (e.g. vcr) high = stable timebase (e.g. broadcast/dvd-source) d4 fidt identi?cation bit for detected ?eld frequency; low = 50 hz, high = 60 hz d5 hlvln status bit for horizontal and vertical loop: low = both loops locked, high = unlocked d6 intl status bit for interlace detection, low = non interlaced, high = interlaced d7
preliminary nda required con?dential - nda required page 158 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.3 programming register audio clock generation see equations in chapter 8.6 and examples on table 28 on page 83, table 30 on page 85 and table 31 on page 87 16.3.1 s ubaddresses 30 to 32 amclk c ycles per f ield table 92 audio master clock: cycles per ?eld (sa 30, sa 31, sa 32) 16.3.2 s ubaddresses 34 to 36 amclk n ominal i ncrement table 93 audio master clock: nominal increment (sa 34, sa 53, sa 36) 16.3.3 s ubaddress 38 r atio amxclk to asclk table 94 clock ratio audio master clock to serial clock (bit clock) asclk (sa 38) 16.3.4 s ubaddress 39 r atio asclk to alrclk table 95 clock ratio serial clock asclk to alrclk (channel select clock) (sa 39) audio master clock: cycles per field control bits d7 to d0 sa 30 acpf7 acpf6 acpf5 acpf4 acpf3 acpf2 acpf1 acpf0 sa 31 acpf15 acpf14 acpf13 acpf12 acpf11 acpf10 acpf9 acpf8 sa 32 acpf17 acpf16 audio master clock: nominal increment control bits d7 to d0 sa 34 acni7 acni6 acni5 acni4 acni3 acni2 acni1 acni0 sa 35 acni15 acni14 acni13 acni12 acni11 acni10 acni9 acni8 sa 36 acni21 acni20 acni19 acni18 acni17 acni16 clock ratio audio master clock to serial clock control bits d5 to d0 sa 38 sdiv5 sdiv4 sdiv3 sdiv2 sdiv1 sdiv0 refer to chapter 8.7 clock ratio serial clock asclk to alrclk control bits d5 to d0 sa 39 lrdiv5 lrdiv4 lrdiv3 lrdiv2 lrdiv1 lrdiv0 refer to chapter 8.7
preliminary nda required con?dential - nda required page 159 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.3.5 s ubaddress 3a a udio c lock c ontrol table 96 audio clock control (sa 3a) function name levels bits asclk phase asclk edges triggered by falling edges of amclk scph 0 d0 asclk edges triggered by rising edges of amclk 1 alrclk phase alrclk edges triggered by falling edges of asclk lrph 0 d1 alrclk edges triggered by rising edges of asclk 1 audio master clock vertical reference vertical reference pulse is taken from internal decoder amvr 0 d2 vertical reference is taken form xrv-input (expansion port) 1 audio pll mode pll active, amclk is frame-locked to the incoming video signal (vertical reference pulse) apll 0 d3 pll open, amclk is free running 1 audio pll mode (only active if ucgc = 1) internal audio master clock is divided by 4 cgcdiv 0 d6 internal audio master clock is divided by 3 1 audio clock: cgc generation mode second cgc (cgc2) bypassed (e.g. in case cgc2 is used for scaler backend clock generation): audio clock as generated by the audio pll is output on pin amclk ucgc 0 d7 second cgc (cgc2) in use for audio clock generation: enhances the jitter, performance of the generated audio master clock on pin amclk 1
preliminary nda required con?dential - nda required page 160 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.4 programming register vbi data slicer 16.4.1 s ubaddress 40 b asic s licer s ettings table 97 amplitude searching (sa 40) table 98 framing code error (sa 40) table 99 hamming check (sa 40) slicer set (40h) d4 amplitude searching control bit hunt_n amplitude searching active [default] 0 amplitude searching stopped 1 slicer set (40h) d5 framing code error control bit fce one framing code error allowed 0 no framing code errors allowed 1 slicer set (40h) d6 hamming check control bit ham_n hamming check for 2 bytes after framing code, depending on data type [default] 0 no hamming check 1
preliminary nda required con?dential - nda required page 161 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 100 wss-check (sa 40) slicer set (40h) d7 wss525 crc code check (1) 1. the vbi slicer will only track the amplitude of data that it considers to be valid; this tracking is important for optimal acquisition performance. if no valid data is found for several successive frames, then the slicer will enter amplitude searching (hunting) mode until valid data is found again. chkwss alters the definition of "valid" data. side effect if 1: if wss525 data is present but containing incorrect crc bits, the slicer will enter hunting mode, and acquisition may intermittently fail even with an undistorted signal. side effect if 0: if the slicer is set to acquire wss525 from lines containing noise, or another data type, then false detections of "valid" data are more likely to occur which will upset the amplitude tracking mechanism. (note that hunting can still occur if the wss525 start bits are never detected.) control bit chkwss all wss525 packets are considered valid (provided that the start bit is detected), regardless of crcerr 0 only wss525 packets with crcerr = 0 are considered valid 1
preliminary nda required con?dential - nda required page 162 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.4.2 s ubaddress 41 to 57 l ine c ontrol r egister table 101 lcr register 2...24 (sa41 .... sa57) 16.4.3 s ubaddress 58 p rogrammable f raming c ode table 102 framing code for programmable data types (sa58) lcr register 2...24 (41h ....57h) (1) 1. line control register lcr0 to lcr23 are assigned to one vbi dataline of a vbi region each. line control register lcr24 is assigned to all other vbi data lines / active video lines. d7..d4 d3..d0 60hz / 525 lines standards 50hz / 625 lines standards dt[3:0] ?eld 1 dt[3:0] ?eld 2 do not acquire (active video) do not acquire (active video) 0000 0000 us teletext (wst525) euro teletext (wst625) 0001 0001 nabts euro teletext with progammable framing code 0010 0010 moji reserved 0011 0011 us closed caption (cc525) euro closed caption (cc625) 0100 0100 cgms (wss525) euro wide screen signalling (wss625) 0101 0101 vitc525 vitc625 0110 0110 gemstar2x vps 0111 0111 gemstar1x reserved 1000 1000 reserved reserved 1001 1001 open1 (5 mhz) open1 (5 mhz) 1010 1010 open2 (5,7272 mhz) open2 (5,7272 mhz) 1011 1011 reserved reserved 1100 1100 do not acquire (raw) do not acquire (raw) 1101 1101 do not acquire (test) do not acquire (test) 1110 1110 do not acquire (active video) do not acquire (active video) 1111 1111 slicer set (580h) d7...0 framing code for programmable data types according to the dt table control bits fc7...0 [default] 40h
preliminary nda required con?dential - nda required page 163 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.4.4 s ubaddress 59 h orizontal o ffset table 103 horizontal offset (sa 59, sa 5b) 16.4.5 s ubaddress 5a v ertical o ffset table 104 vertical offset (sa 5a, sa 5b) 16.4.6 s ubaddress 5b f ield o ffset , msb s h/v-o ffsets table 105 field offset, msbs for vertical and horizontal offsets (sa 5b) slicer set (59h, 5bh) 5bh,d2...0 59h,d7...0 horizontal offset control bits control bits hoff10...8 hoff7...0 recommended value 3h 47h slicer set (5ah, 5bh) 5bh,d4 5ah,d7...0 vertical offset control bit control bits voff[8] voff[7:0] minimum value 0 0 0 maximum value 312 1 38 value for 50 hz/625 lines input 0 03 value for 60 hz/525 lines input and itu656 line counting (1) 1. for 60 hz offsets; please refer to sect.8.2 and sect.8.4 006 value for 60 hz/525 lines input and consistent ?eld id (1) 003 slicer set (5bh) d5 vertical trigger edge control bit vep vbi slicer triggers on the negative edge of the internal v123 v-sync (default) 0 vbi slicer triggers on the positive edge of the internal v123 v-sync 1
preliminary nda required con?dential - nda required page 164 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 106 field offset, msbs for vertical and horizontal offsets (sa 5b) slicer set (5bh) d7 field offset control bit foff no modi?cation of internal ?eld indicator, (default for 50 hz/625 lines input sources) 0 invert ?eld indicator (default for 60 hz/525 lines input sources) 1
preliminary nda required con?dential - nda required page 165 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.4.7 s ubaddress 5d: sldom c odes table 107 sliced data output modes (sa 5d) slicer set (5dh) d4 d3 d2 d1 d0 sliced data output mode sldom4 sldom3 sldom2 sldom1 sldom0 output from vbi slicer through i-port is disabled (vitx[1] function of saa7114) x 0 0 0 0 no recoding x x x x 0 recode data values 00h and ffh to even parity values 03h and fch x x x x 1 anc header with constant did byte, programmable via sdid (addr. 5eh) x 0 0 1 x anc header (vip-did) for dt 1 - 8, a and b plus timing codes (empty packages) for lines 1 and after line 23 x 0 1 0 x anc header (vip-did) for dt 1 - 8, a and b no timing codes x 0 1 1 x sav-eav framed output lines, with d2 as t-bit of sav/eav byte x 1 t (1) 1. corresponds to the t-bit of sav/eav codes x x sav-eav framing for the de?ned vbi standards of dt 1 - 8, a and b and dt 9 x 1 t (1) 0 x sav-eav framing for the de?ned vbi standards except for those data types which are accessible via i2c readback registers. suppressed standards are: cc525/625, wss525/625 (cgms), gemstar1x/gemstar2x x 1 t (1) 1 x if regions overlap, output of sliced vbi and scaled video for a certain line 0 1 t (1) x x if regions overlap, output of video is suppressed for sav-eav framed sliced vbi lines 1 1 t (1) x x
preliminary nda required con?dential - nda required page 166 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.4.8 s ubaddress 5e sdid codes table 108 sdid codes (sa 5e) 16.4.9 s ubaddress 5e ( read - only register ) table 109 slicer status bit (sa 5e), read only table 110 slicer status bit (sa 5e), read only slicer set (5eh) d5 d4 d3 d2 d1 d0 sdid codes sdid5 sdid4 sdid3 sdid2 sdid1 sdid0 sdid5..0 = 0h [default] 000000 slicer status bit (5eh) read only d7 framing code valid control bit fc8v no framing code (0 error) in the last frame detected 0 framing code with 0 error detected 1 slicer status bit (5eh) read only d6 framing code valid control bit fc7v no framing code (1 error) in the last frame detected 0 framing code with 1 error detected 1
preliminary nda required con?dential - nda required page 167 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.4.10 s ubaddress 66 to 7f i 2 cr eadback of decoded vbi d ata ( read - only register ) 16.4.10.1 subaddress 66 to 6a i 2 c readback of closed caption data (cc525 and cc625) (read-only register) table 111 closed caption (cc525 and cc625) i 2 c readback (66h, ... , 6ah) read only table 112 closed caption (cc525 and cc625) data order in wss i 2 c readback registers register content (1) 1. all decoded vbi data is written into the registers starting with the lsb of each register first until all data is stored reg. addr. d7 d6 d5 d4 d3 .. d0 status header 66 h cch_7 cch_6 cch_5 cch_4 cch_3 .. cch_0 odd ?eld even ?eld free running ?eld counter being updated data erroneous being updated data erroneous cc payload data byte 1 of odd ?eld 67 h cco1_7 .. cco1_0 cc payload data byte 2 of odd ?eld 68 h cco2_7 .. cco2_0 cc payload data byte 1 of even ?eld 69 h cce1_7 .. cce1_0 cc payload data byte 2 of even ?eld 6a h cce2_7 .. cce2_0 register name cco1 / cce1 cco2 / cce2 register addr. 6c h / 6f h 6d h / 70 h register bit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 cc525 bit no. (1) 1. cc data bits in order they appear in the vbi data line (beginning with bit 0) 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 cc625 bit no. (1) 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
preliminary nda required con?dential - nda required page 168 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.4.10.2 subaddress 6b to 71 i 2 c readback of closed caption data (wss525 and wss625) (read-only register) table 113 widescreen signalling (wss525 and wss625) i 2 c readback (6bh, ... , 71h) read only table 114 widescreen signalling (wss525 and wss625) data order in wss i 2 c readback registers register content (1) 1. all decoded vbi data is written into the registers starting with the lsb of each register first until all data is stored reg. addr. d7 d6 d5 d4 d3 .. d0 status header 6b h wssh_7 wssh_6 wssh_5 wssh_4 wssh_3 .. wssh_0 odd ?eld even ?eld free running ?eld counter being updated data erroneous being updated data erroneous wss payload data byte 1 of odd ?eld 6c h wsso1_7 .. wsso1_0 wss payload data byte 2 of odd ?eld 6d h wsso2_7 .. wsso2_0 wss payload data byte 2 of odd ?eld 6e h wsso3_7 .. wsso3_0 wss payload data byte 1 of even ?eld 6f h wsse1_7 .. wsse1_0 wss payload data byte 2 of even ?eld 70 h wsse2_7 .. wsse2_0 wss payload data byte 3 of even ?eld 71 h wsse3_7 .. wsse3_0 register name wsso1 / wsse1 wsso2 / wsse2 wsso3 / wsse3 register addr. 6c h / 6f h 6d h / 70 h 6e h / 71 h register bit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 wss525 bit no. (1) 1. wss525 data bits in order they appear in the vbi data line (beginning with bit 1) 8 7 6 5 4 3 2 1 16 15 14 13 12 11 10 9 c (2) 2. this bit carries the result of the crc-check. it is 0 if the received crc code is identical to the calculated crc code, else it is set to 1 - - - 20 19 18 17 wss625 bit no. (3) 3. wss625 data bits in order they appear in the vbi data line (beginning with bit 0) 7 6 5 4 3 2 1 0 - - 13 12 11 10 9 8 - - - - - - - -
preliminary nda required con?dential - nda required page 169 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.4.10.3 subaddress 72 to 76 i 2 c readback of gemstar1x data (read-only register) table 115 gemstar1x i 2 c readback (72h, ... , 76h) read only table 116 gemstar 1x data order in gemstar 1x i 2 c readback registers register content (1) 1. all decoded vbi data is written into the registers starting with the lsb of each register first until all data is stored reg. addr. d7 d6 d5 d4 d3 .. d0 status header 72 h gs1h_7 gs1h_6 gs1h_5 gs1h_4 gs1h_3 .. gs1h_0 odd ?eld even ?eld free running ?eld counter being updated data erroneous being updated data erroneous gs1 payload data byte 1 of odd ?eld 73 h gs1o1_7 .. gs1o1_0 gs1 payload data byte 2 of odd ?eld 74 h gs1o2_7 .. gs1o2_0 gs1 payload data byte 1 of even ?eld 75 h gs1e1_7 .. gs1e1_0 gs1 payload data byte 2 of even ?eld 76 h gs1e2_7 .. gs1e2_0 register name gs1o1 / gs1e1 gs1o2 / gs1e2 register addr. 73 h / 75 h 74 h / 76 h register bit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 gemstar 1x bit no. (1) 1. gemstar 1x data bits in order they appear in the vbi data line (beginning with bit 0) 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
preliminary nda required con?dential - nda required page 170 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.4.10.4 subaddress 77 to 7f i 2 c readback of gemstar2x data (read-only register) table 117 gemstar2x i 2 c readback (77 h, ... , 7f h) read only table 118 gemstar 2x data order in gemstar 2x i 2 c readback registers register content (1) 1. all decoded vbi data is written into the registers starting with the lsb of each register first until all data is stored reg. addr. d7 d6 d5 d4 d3 .. d0 status header 77 h gs2h_7 gs2h_6 gs2h_5 gs2h_4 gs2h_3 .. gs2h_0 odd ?eld even ?eld free running ?eld counter being updated data erroneous being updated data erroneous gs2 payload data byte 1 of odd ?eld 78 h gs2o1_7 .. gs2o1_0 gs2 payload data byte 2 of odd ?eld 79 h gs2o2_7 .. gs2o2_0 gs2 payload data byte 2 of odd ?eld 7a h gs2o3_7 .. gs2o3_0 gs2 payload data byte 2 of odd ?eld 7b h gs2o4_7 .. gs2o4_0 gs2 payload data byte 1 of even ?eld 7c h gs2e1_7 .. gs2e1_0 gs2 payload data byte 2 of even ?eld 7d h gs2e2_7 .. gs2e2_0 gs2 payload data byte 3 of even ?eld 7e h gs2e3_7 .. gs2e3_0 gs2 payload data byte 4 of even ?eld 7f h gs2e3_7 .. gs2e3_0 register name gs2o1 / gs2e1 gs2o2 / gs2e2 gs2o1 / gs2e1 gs2o2 / gs2e2 register addr. 78 h / 7c h 79 h / 7d h 7a h / 7e h 7b h / 7f h register bit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 gemstar 2x bit no. (1) 1. gemstar 2x data bits in order they appear in the vbi data line (beginning with bit 0) 7 6 5 4 3 2 1 0 1 5 1 4 1 3 1 2 1 1 1 0 9 8 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4
preliminary nda required con?dential - nda required page 171 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.5 programming register - interfaces and scaler part 16.5.1 s ubaddress 80: g lobal s ettings table 119 continuous mode (continuous ?eld mode) (sa 80) table 120 task enable control (sa 80) global set (80h) d7 continuous ?eld mode control bit cmod ?eld processing is done according the trigger conditions and window de?nitions of an enabled programming page 0 permanent processing of the enabled task according to teb (0x80) and tea (0x80) settings until sw reset of the scaler. the vertical window de?nitions are ignored and the selected v-sync (see v_eav1,veav0) de?nes the blanking interval 1 global set (80h) d5 d4 task enable control control bits control bits teb tea task of register set a is disabled x 0 task of register set a is enabled x 1 task of register set b is disabled 0 x task of register set b is enabled 1 x
preliminary nda required con?dential - nda required page 172 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 121 i-port and scaler backend clock selection (sa 80) global set (80h) d3 d2 d1 d0 i - port and scaler backend clock selection control bits mode i-port output clock scaler backend clock icks 3 icks 2 icks 1 icks 0 8-bit output mode (byte) at full clock rate: - full data rate at full clock rate line locked clock from decoder pll 0 0 0 0 input clock at xclk input of the x-port 0 0 0 1 clock from feature pll (pll2) 0 0 1 0 external input clock from iclk 0 0 1 1 general 16-bit output mode: - full data rate at full clock rate luminance data (y) at ipd[7:0] output pins and decoded chrominance data (cb,cr) at hpd[7:0] output pins line locked clock from decoder pll 0 1 0 0 input clock at xclk input of the x-port 0 1 0 1 clock from feature pll (pll2) 0 1 1 0 external input clock from iclk 0 1 1 1 dmsd2-legacy 16-bit output mode - half data rate at half clock rate luminance data (y) at ipd[7:0] output pins, decoded chrominance data (cb,cr) at hpd[7:0] output pins cref function is provided on in idq. as an alternative idq can also be used as clock (adjustable delay via ipck[3:2]) line locked clock from decoder pll line locked clock / 2 from decoder pll 1 0 0 0 input clock at xclk input of the x-port input clock at xclk input of the x-port divided by 2 1 0 0 1 clock from feature pll (pll2) clock from feature pll (pll2) divided by 2 1 0 1 0 external input clock from iclk external input clock from iclk divided by 2 1 0 1 1 zoomed video 16-bit output mode: - half data rate at half clock rate (luminance data (y) at ipd[7:0] output pins, decoded chrominance data (cb,cr) at hpd[7:0] output pins) idq obsolete line locked clock / 2 from decoder pll 1 1 0 0 input clock at xclk input of the x-port divided by 2 1 1 0 1 clock from feature pll (pll2) divided by 2 1 1 1 0 reserved 1 1 1 1
preliminary nda required con?dential - nda required page 173 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 122 vertical sync and field id source selection (sa 81) table 123 characteristic of the retimed v and f signals (sa 81) 16.5.2 s ubaddress 83 to 87: g lobal i nterface c onfigurations table 124 x-port output clock phase control (sa 83) global set (81h) d1 d0 vertical sync and field id source selection for the generation of v- and f-bit in sav / eav codes and the v-sync and fid function on pins igpv and igp0/1 control bits control bits v_eav1 v_eav0 v-blanking signal from scaler input (vblnk_ccir from decoder or xrv from x-port) with corresponding field id (even_ccir or detected from x-port) 0 0 programmable v-gate signal vgate_l from decoder (see vsta,vsto reg. 0x15 and 0x16 of decoder part) or xrv from x-port with corresponding field id (but detected id from x-port shifted by one line) 0 1 lcr table controlled v-gate and field id from the text data path 1 0 conlv controlled region and page dependent v-gate from scaler data path, field id is snatched to scalers v-trigger (see v123 timing) 1 1 global set (81h) d2 change of 1/2 line characteristic of the retimed v and f signals (see igpv and igp0/1 functions, signals vs_i and fid_i ) control bits ftime fid 0 -> v-edge after end of line (eol), fid change 0->1 after start of line (sol) fid 1 -> v-edge after sol, fid change 1->0 after eol 0 upper v and fid timing characteristics change from eol to sol and .vv. 1 global set (83h) d5 d4 x-port output clock phase control control bits control bits xpck1 xpck0 xclk inverted input/output phase 0 0 recommended setting, if xclk-pin is used as input 0 1 iclk inverted and phase shifted by about 3 nsec 1 0 recommended setting, if xclk-pin is used as output 1 1
preliminary nda required con?dential - nda required page 174 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 125 x-port i/o enable control (sa 83) table 126 i-port output signal de?nitions igph / igpv (sa 84) global set (83h) d2 d1 d0 x-port i/o enable control, controls pins xpd[7:0], xdq, xrh, xrv and xclk control bits control bits control bits xrqt xpe1 xpe0 x - port output is disabled by software x 0 0 x - port output is enabled by software x 0 1 x - port output is enabled by pin xtri at 0 x 1 0 x - port output is enabled by pin xtri at 1 x 1 1 xrdy output signal is a/b task ?ag from event handler (a = 1) 0xx xrdy output signal is ready signal from scaler path (xrdy = 1 means scaler is ready to receive data) 1xx global set (84h) d3 d2 d1 d0 i - port output signal de?nitions igph / igpv control bits control bits control bits control bits idv1 idv0 idh1 idh0 igph is a h -gate signal, framing the scaler output x x 0 0 igph is an extended h-gate (framing h-gate during scaler output and scaler input h-reference outside the scaler window) xx01 igph is a horizontal trigger pulse on the rising edge of h-gate xx10 igph is a horizontal trigger pulse on the rising edge of extended h-gate xx11 igpv is a v - gate signal as de?ned by v_eav[81[1:0]] 0 0 x x igpv is a v-sync like signal, as de?ned by v_eav, with emulated 1/2 line characteristic (vs_i) 01xx igpv is a vertical trigger pulse on the rising edge of the v-gate 10x igpv is a vertical trigger pulse on the rising edge of the v-sync like signal 11xx
preliminary nda required con?dential - nda required page 175 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 127 i-port signal de?nitions igp0 (sa 84) table 128 i-port signal de?nitions igp1 (sa 84) global set (84h and 86h) 86h d4 84h d5 84h d4 i - port signal de?nitions igp0 control bits control bits control bits idg02 idg01 idg00 igp0 is output ?eld id, as de?ned by v_eav[81[1:0]] 0 0 0 igp0 is a ?eld id, as de?ned by v_eav and ftime[81[2]], with emulated 1/2 line characteristic (fid_i) 0 0 1 igp0 is sliced data ?ag, framing the sliced vbi data at the i-port 0 1 0 igp0 is a/b task ?ag, as de?ned by conlh [90[7]] 0 1 1 igp0 is the output fifo almost ?lled ?ag 1 0 0 igp0 is the output fifo almost full ?ag, level to be programmed in addr. 86h 1 0 1 igp0 is the output fifo almost empty ?ag, level to be programmed in addr. 86h 1 1 0 igp0 is set to 0 (default polarity) 1 1 1 global set (84h and 86h) 86h d5 84h d7 84h d6 i - port signal de?nitions igp1 control bits control bits control bits idg12 idg11 idg10 igp1 is output ?eld id, as de?ned by v_eav[81[1:0]] 0 0 0 igp1 is a ?eld id, as de?ned by v_eav and ftime[81[2]], with emulated 1/2 line characteristic (fid_i) 0 0 1 igp1 is sliced data ?ag, framing the sliced vbi data at the i-port 0 1 0 igp1 is a/b task ?ag, as de?ned by conlh [90[7]] 0 1 1 igp1 is the output fifo almost ?lled ?ag 1 0 0 igp1 is the output fifo almost full ?ag, level to be programmed in addr. 86h 1 0 1 igp1 is the output fifo almost empty ?ag, level to be programmed in addr. 86h 1 1 0 igp1 is set to 0 (default polarity) 1 1 1
preliminary nda required con?dential - nda required page 176 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 129 i-port reference signal polarities (sa 85) global set (85h) d4 d3 d2 d1 d0 i - port reference signal polarities control bits control bits control bits control bits control bits igp1p igp0p irvp irhp idqp idq at default polarity (1 active) xxxx0 idq is inverted xxxx1 igph at default polarity (1 active) x x x 0 x igph is inverted x x x 1 x igpv at default polarity (1 active) x x 0 x x igpv is inverted x x 1 x x igp0 at default polarity x 0 x x x igp0 is inverted x 1 x x x igp1 at default polarity 0 xxxx igp1 is inverted 1 xxxx
preliminary nda required con?dential - nda required page 177 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 130 i-port signal de?nitions (sa 85) table 131 i-port signal de?nitions (sa 86) global set (85h) d7 d6 d5 i - port signal de?nitions ipd[7:0] (hpd[7:0]) control bits control bits control bits iswp1 iswp0 illv video data limited to range 1 to 254 x x 0 video data limited to range 8 to 247 x x 1 d-word byte swap, in?uences serial output timing d0 d1 d2 d3 => ff 00 00 sav cb0 y0 cr0 y1 00x d1 d0 d3 d2 => 00 ff sav 00 y0 cb0 y1 cr0 0 1 x d2 d3 d0 d1 => 00 sav ff 00 cr0 y1 cb0 y0 1 0 x d3 d2 d1 d0 => sav 00 00 ff y1 cr0 y0 cb0 1 1 x global set (86h) d3 d2 d1 d0 i - port signal de?nitions control bits control bits control bits control bits ffl1 ffl0 fel1 fel0 fae ?fo ?ag almost empty level < 16 d-words xx00 < 8 d-words x x 0 1 < 4 d-words x x 1 0 = 0 d-words x x 1 1 faf ?fo ?ag almost full level >= 16 d-words 00xx >= 24 d-words 0 1 x x >= 28 d-words 1 0 x x = 32 d-words 1 1 x x
preliminary nda required con?dential - nda required page 178 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 132 i-port packing mode (continuous pixel mode) (sa 86) table 133 i-port signal de?nitions,ffd1,0 (sa 86) global set (86h) d7 i-port packing mode control bit impak data packing controlled by itrdy pin 0 data packing is done internally, by href synchronous delayed trigger pulses. the trigger delay can be de?ned per active data type (data of page a, page b and data of text path c). trigger signals are generated by the pulse generator (see reg. f6h to fbh parameters pghaps, pghbps, pghcps) 1 global set (86h) d6 i - port signal de?nitions, ffd1,0 related to subaddr. 84 control bits vitx i-port video data output is inhibited 0 i-port video data are transferred 1 note: text data transfer is now controlled by new sldom control byte (reg. 0x5d)
preliminary nda required con?dential - nda required page 179 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 134 i-port output clock and gated clock phase control (sa 87) table 135 i-port i/o control (sa 87) global set (87h) d7 d6 d5 d4 i-port input/output clock and gated clock phase control (idq, iclk) control bits control bits control bits control bits ipck3 ipck2 ipck1 ipck0 iclk inverted input/output phase x x 0 0 recommended setting, if iclk-pin is used as input x x 0 1 iclk inverted and phase shifted by about 3 nsec x x 1 0 recommended setting, if iclk-pin is used as output x x 1 1 note: ipck[3:2] only effects the gated clock or quali?er on pin idq in dmsd-legacy mode (see also addr. 80h, icks[3:0]) tbf 0 0 x x tbf 0 1 x x tbf 1 0 x x tbf 1 1 x x global set (87h) d1 d0 i-port i/o control (ipd[7:0], idq, igph, igpv, igp0, igp1) control bits control bits ipe1 ipe0 i - port output is disabled by software (including the h-port hpd[7:0] if used as 16-bit extension for the i-port) 00 i - port output is enabled by software 0 1 i - port output is enabled by pin itri at 0 1 0 i - port output is enabled by pin itri at 1 1 1
preliminary nda required con?dential - nda required page 180 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.5.3 s ubaddress 88: s leep and p ower save control table 136 power save control (sa 86) table 137 adc-port output control/ startup control (sa 88) global set (88h) d3 d1 d0 power save control control bits control bits control bits slm3 slm1 slm0 decoder and vbi slicer are in operational mode x x 0 decoder and vbi slicer are in power down note: scaler only operates, if scaler input and iclk source is the x-port (refer to addr. 80h and 91/c1h) xx1 scaler is in operational mode x 0 x scaler is in power down note: scaler in power down stops i-port output!! x1x audio clock generation active 0 x x audio clock generation in power down and output disabled 1 x x global set (88h) d7 d6 d5 d4 adc-port output control/ startup control control bits control bits control bits control bits ch2en ch1en swrst dprog dprog =0 after reset dprog = 1, can be used to assign that the device has been programmed.this bit can be monitored in the scalers status byte, bit prdon. if dprog was set to 1 and prdon status bit shows a 0 a power or startup fail has occurred xxx0 xxx1 scaler path is reset to its idle state, software reset x x 0 x scaler is switched back to operation x x 1 x ad1x analog channel is in power-down mode x 0 x x ad1x analog channel is active x 1 x x ad2x analog channel is in power-down mode 0 x x x ad2x analog channel is active 1 x x x
preliminary nda required con?dential - nda required page 181 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.5.4 s ubaddress 8f ( read - only register ): status information scaler part table 138 status information scaler bits (sa 8f) 16.5.5 s ubaddress 90: event handler control table 139 event handler control (sa 90; sa c0) i 2 c-bus status bits note: status info is unsynchronized and shows the actual status at the time of iic-read function data bit fidsco status of the ?eld sequence id at the scalers output, scaler processing dependent d0 fidsci status of the ?eld sequence id at the scalers input d1 err_of error ?ag of scalers output formatter, normally set, if the output processing needs to be interrupted, due to input/output data rate con?icts, e.g. if output data rate is much too low and all internal fifo capacity used d2 prdon copy of bit dprog, can be used to detect power up and start up fails d3 ffov status of the internal fifo over?ow ?ag d4 ffil status of the internal fifo almost ?lled ?ag d5 itri status on input pin itri, if not used for tri-state control, usable as hardware ?ag for software use d6 xtri status on input pin xtri, if not used for tri-state control, usable as hardware ?ag for software use d7 register set a (90h) and b (c0h) d2 d1 d0 event handler control control bits control bits control bits rptsk strc1 strc0 event handler triggers immediately after ?nishing a task x 0 0 event handler triggers with next v sync x 0 1 event handler triggers with ?eld id = 0 x 1 0 event handler triggers with ?eld id = 1 x 1 1 if active task is ?nished, handling is taken over by the next task 0xx active task is repeated once, before handling is taken over by the next task 1xx
preliminary nda required con?dential - nda required page 182 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 140 event handler control (sa 90; sa c0) table 141 event handler control (sa 90; sa c0) 16.5.6 s ubaddress 91 to 93: scaler input and i- port output configuration table 142 scaler input format and con?gurationformat control (sa 91; sa c1) register set a (90h) and b (c0h) d5 d4 d3 event handler control control bits control bits control bits fskp2 fskp1 fskp0 active task is carried out directly 0 0 0 1 ?eld is skipped before active task is carried out 0 0 1 .. ?elds are skipped before active task is carried out .. .. .. 6 ?elds are skipped before active task is carried out 1 1 0 7 ?elds are skipped before active task is carried out 1 1 1 register set a (90h) and b (c0h) d7 d6 event handler control control bits control bits conlh ofidc output ?eld id is ?eld id from scaler input x 0 output ?eld id is task status ?ag, which changes every time an selected task is activated (not synchronized to input ?eld id) x1 scaler sav/eav byte bit d7 and task ?ag = 1, default 0 x scaler sav/eav byte bit d7 and task ?ag = 0 1 x register set a (91h) and b (c1h) d2 d1 d0 scaler input format and con?guration format control control bits control bits control bits fsc2 fsc1 fsc0 input is yuv 4:2:2 like sampling scheme x x 0 input is yuv 4:1:1 like sampling scheme x x 1 fsc[2:1] only to be used, if x-port input source dont provide chroma information for every input line (note: x-port input stream must contain dummy chroma bytes) chroma is provided every line, default 0 0 x chroma is provided every 2nd line 0 1 x chroma is provided every 3rd line 1 0 x chroma is provided every 4th line 1 1 x
preliminary nda required con?dential - nda required page 183 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 143 scaler input format and con?gurationsource selection (sa 91; sa c1) table 144 x-port input reference signal de?nitions (sa 92; sa c2) register set a (91h) and b (c1h) d7 d6 d5 d4 d3 scaler input format and con?guration source selection control bits control bits control bits control bits control bits conlv hldfv scsrc1 scsrc0 scrqe only if xrqt subaddr. 83 = 1: scaler input source reacts on 7115 request xxxx0 scaler input source is a continuous data stream, which can not be interrupted (must be 1, if 7115 decoder part is source of scaler or xrqt subaddr.83 = 0) xxxx1 scaler input source is data from decoder, data type is provided according to table table 6 on page 43 xx00x scaler input source is yuv data from x-port xx01x scaler input source is raw digital cvbs from selected analog channel, for backward compatibility only, further use is not recommended xx10x scaler input source is raw digital cvbs (or 16 bit y + uv, if no 16 bit output are active) from x-port xx11x sav/eav code bits d6 and d5 (f and v) may change between sav and eav x0xxx sav/eav code bits d6 and d5 (f and vbit) are synchronized to scalers output line start x1xxx sav/eav code bit d5 (v-bit) and v-gate on pin igpv as generated by the internal processing, see fig.38 0xxxx sav/eav code bit d5 (v-bit) and v-gate are inverted 1 xxxx register set a(92h) and b (c2h) d3 d2 d1 d0 x - port input reference signal de?nitions control bits control bits control bits control bits xcode xdh xdq xcks xclk input clock and xdq input quali?er are needed x x x 0 data rate is de?ned by xclk only, no xdq signal used x x x 1 data are quali?ed at xdq input at 1 x x 0 x data are quali?ed at xdq input at 0 x x 1 x rising edge of xrh input is horizontal reference x 0 x x falling edge of xrh input is horizontal reference x 1 x x reference signals are taken from xrh and xrv 0 x x x reference signals are decoded from eav and sav 1 x x x
preliminary nda required con?dential - nda required page 184 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 145 scaler input reference signal de?nitions (sa 92; sa c2) table 146 i-port output formats and con?guration (sa 93; sa c3) register set a(92h) and b (c2h) d7 d6 d5 d4 scaler input reference signal de?nitions control bits control bits control bits control bits xfdv xfdh xdv1 xdv0 rising edge of xrv input and decoder v123 is vertical reference xxx0 falling edge of xrv input and decoder v123 is vertical reference xxx1 xrv is a v- sync or v-gate signal x x 0 x xrv is a frame sync, v - pulses are generated internally on both edges of fs input xx1x x-port ?eld id is state of xrh at reference edge on xrv (de?ned by xfdv) x0xx ?eld id (decoder and x-port ?eld id) is inverted x 1 x x reference edge for ?eld detection is falling edge of xrv 0 x x x reference edge for ?eld detection is rising edge of xrv 1 x x x register set a(93h) and b (c3h) d4 d3 d2 d1 d0 i - port output formats and con?guration control bits control bits control bits control bits control bits foi1 foi0 fsi2 fsi1 fsi0 4:2:2 d word formatting x x 0 0 0 4:1:1 d word formatting x x 0 0 1 4:2:0, only every 2nd line y + uv output, in between y only output xx010 4:1:0, only every 4th line y + uv output, in between y only output xx011 y only x x 1 0 0 not de?ned x x 1 0 1 not de?ned x x 1 1 0 not de?ned x x 1 1 1 number of leading y only lines, before 1rst y + uv line is output: 00 = no leading y only line .. 11= 3 leading y only lines 00xxx 01xxx 10xxx 11xxx
preliminary nda required con?dential - nda required page 185 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 147 i-port output formats and con?guration (sa 93; sa c3) 16.5.7 s ubaddress 94 to 9b: s caler i nput a cquisition w indow d efinition table 148 horizontal input acquisition window de?nition offset (sa 94, sa95; sa c4, sac5) table 149 horizontal input acquisition window de?nition input window length (sa 96, sa97; sa c6, sac7) register set a (93h) and b (c3h) d7 d6 d5 i - port output formats and con?guration control bits control bits control bits icode ins80 fysk all lines will be output x x0 skip the number of leading y only lines, as de?ned by foi1,0 x x1 remaining blanking intervals and cycles with invalid data are ?lled with 0x00 x 0 x remaining blanking intervals are ?lled with 0x80 for chroma and 0x10 for luma bytes and data are hold during cycles with invalid data x 1 x no itu656 like sav,eav codes are available 0 xx itu656 like sav,eav codes are inserted in the output data stream, framed by a quali?er 1 xx register set a (94h ....95h) and b (c4h ... c5h) 95h / c5h d3 .. d0 94h / c4h d7..d4 94h / c4h d3 .. d0 horizontal input acquisition window de?nition offset in x (horizontal) direction reference for counting are luminance samples xo11..8 xo7..4 xo3..0 a minimum of 2 should be kept, due to a line counting mismatch 0 0 0 0 0 0 0 0 0 0 1 0 odd offsets are changing the uv sequence in the output stream to vu sequence 0 0 0 0 0 0 0 0 0 0 1 1 maximum possible pixel offset = 4095 1 1 1 1 1 1 1 1 1 1 1 1 register set a (96h ....97h) and b (c6h ... c7h) 97h / c7h d3 .. d0 96h / c6h d7..d4 96h / c6h d3 .. d0 horizontal input acquisition window de?nition input window length in x (horizontal) direction reference for counting are luminance samples xs11..8 xs7..4 xs3..0 no output 0 0 0 0 0 0 0 0 0 0 0 0 odd lengths are allowed, but will be rounded up to even lengths 0 0 0 0 0 0 0 0 0 0 0 1 ... ... ... ... maximum possible no. of input pixels = 4095 1 1 1 1 1 1 1 1 1 1 1 1
preliminary nda required con?dential - nda required page 186 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 150 vertical input acquisition window de?nition offset (sa 98, sa99; sa c8, sa c9) table 151 vertical input acquisition window de?nition (sa 9a, sa 9b; sa ca, sa cb) table 152 field processing mode (sa 9a; sacb) register set a (98h ....99h) and b (c8h ... c9h) 99h / c9h d3 .. d0 98h / c8h d7..d4 98h / c8h d3 .. d0 vertical input acquisition window de?nition offset in y (vertical) direction yo11..8 yo7..4 yo3..0 note: for trigger condition (addr. 90, strc[1:0])!= 00 yo + ys > (number of input lines/?eld -2), will result in ?eld dropping 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 maximum line offset = 4095 offsets > (number of input lines/?eld -2) will result in ?eld dropping 1 1 1 1 1 1 1 1 1 1 1 1 register set a (9ah ....9bh) and b (cah ... cbh) 9bh / cbh d3 ..d0 9ah / cah d7..d4 9ah / cah d3 ..d0 vertical input acquisition window de?nition input window length in y (vertical) direction ys11..8 ys7..4 ys3..0 note: for trigger condition (addr. 90, strc[1:0])!= 00 yo + ys > (number of input lines/?eld -2), will result in ?eld dropping 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ... ... ... maximum possible number of input lines = 4095 lengths > (number of input lines/?eld -2) will result in ?eld dropping 1 1 1 1 1 1 1 1 1 1 1 1 register set a (9bh) and b (cbh) d7 field mode (continuous task mode) control bit fmod vertical processing is de?ned by offset and length parameters, if a v trigger occurs before ys input lines are processed ?eld dropping may occur 0 vertical processing is de?ned by start and end line parameters (yo = start line, ys = end line), if a v trigger occurs before end line is reached, the vertical window is cut, if the start line is not reached at v trigger the processing is started, if the trigger occurs inside the de?ned region 1
preliminary nda required con?dential - nda required page 187 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.5.8 s ubaddress 9c to 9f: s caler o utput w indow d efinition table 153 horizontal output acquisition window de?nition (sa 9c, sa 9d; sa cc, sa cd) table 154 vertical output acquisition window de?nition (sa 9e, sa 9f; sa ce, sa cf) register set a (9ch ....9dh) and b (cch ... cdh) 9dh / cdh d3 ..d0 9ch / cch h d7..d4 9ch / cch d3 ..d0 horizontal output acquisition window de?nition number of desired output pixel in x (horizontal) direction reference for counting are luminance samples xd11..8 xd7..4 xd3..0 no output 0 0 0 0 0 0 0 0 0 0 0 0 odd lengths are allowed, but will be ?lled up to even lengths 0 0 0 0 0 0 0 0 0 0 0 1 ... ... ... ... maximum possible number of input pixels= 4095 if the desired output length is greater, than the number of scaled output pixels, the last scaled pixel is repeated 1 1 1 1 1 1 1 1 1 1 1 1 register set a (9eh ....9fh) and b (ceh ... cfh) 9fh / cfh d3 ..d0 9eh / ceh d7..d4 9eh / ceh d3 ..d0 vertical output acquisition window de?nition number of desired output lines in y (vertical)direction yd11..8 yd7..4 yd3..0 no output 0 0 0 0 0 0 0 0 0 0 0 0 1 pixel 0 0 0 0 0 0 0 0 0 0 0 1 ... ... ... ... maximum possible number of output lines = 4095 if the desired output length is greater, than the number of scaled output lines, the processing is cut 1 1 1 1 1 1 1 1 1 1 1 1
preliminary nda required con?dential - nda required page 188 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.5.9 s ubaddress a0 to a2: p rescaling and fir filtering table 155 horizontal integer prescaling ratio xpsc (sa a0; sa d0) table 156 horizontal prescaler accumulation sequence length xacl (sa a1; sa d1) register set a (a0h) and b (d0h) d5 d4 d3 d2 d1 d0 horizontal integer prescaling ratio xpsc control bits control bits control bits control bits control bits control bits xpsc5 xpsc4 xpsc3 xpsc2 xpsc1 xpsc0 !! not allowed !! 000000 down scale = 1 000001 down scale = 1/2 000010 .. .. .. .. .. .. down scale = 1/63 111111 register set a (a1h) and b (d1h) d5 d4 d3 d2 d1 d0 horizontal prescaler accumulation sequence length xacl control bits control bits control bits control bits control bits control bits xacl5 xacl4 xacl3 xacl2 xacl1 xacl0 accu length = 1 000000 accu length = 2 000001 .. .. .. .. .. .. accu length = 64 111111
preliminary nda required con?dential - nda required page 189 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 157 prescaler dc gain and fir pre?lter control (sa a2; sa d2) table 158 prescaler dc gain and fir pre?lter control (sa a2; sa d2) register set a (a2h) and b (d2h) d3 d2 d1 d0 prescaler dc gain and fir pre?lter control control bits control bits control bits control bits xc2_1 xdcg2 xdcg1 xdcg0 prescaler output is renormalized by gain factor = 1 x 0 0 0 gain factor = 1/2 x 0 0 1 gain factor = 1/4 x 0 1 0 gain factor = 1/8 x 0 1 1 gain factor = 1/16 x 1 0 0 gain factor = 1/32 x 1 0 1 gain factor = 1/64 x 1 1 0 gain factor = 1/128 x 1 1 1 weighting of all accumulated samples is factor 1 e.g. xacl = 4 => sequence 1+ 1+ 1+ 1+ 1 0xxx weighting of samples inside sequence is factor 2 e.g. xacl = 4 => sequence 1+ 2+ 2+ 2+ 1 1xxx register set a (a2h) and b (d2h) d7 d6 d5 d4 prescaler dc gain and fir pre?lter control control bits control bits control bits control bits pfuv1 pfuv0 pfy1 pfy0 luminance fir ?lter bypassed x x 0 0 h_y(z) = 1/4 * (1 2 1) x x 0 1 h_y(z) = 1/8 * (-1 1 1.75 4.5 1.75 1 -1) x x 1 0 h_y(z) = 1/8 * ( 1222 1) x x 1 1 chrominance fir ?lter bypassed 0 0 x x h_uv(z) = 1/4 * (1 2 1) 0 1 x x h_uv(z) = 1/32 * (3 8 10 8 3) 1 0 x x h_uv(z) = 1/8 * (1 2 2 2 1) 1 1 x x
preliminary nda required con?dential - nda required page 190 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.5.10 s ubaddress a4 to a6: b rightness ,c ontrast and s aturation c ontrol table 159 luminance brightness setting (sa a4; sa d4) table 160 luminance contrast setting (sa a5; sa d5) table 161 chrominance saturation setting (sa a6; sa d6) register set a (a4h) and b (d4h) d7 d6 d5 d4 d3 d2 d1 d0 luminance brightness setting control bits control bits control bits control bits control bits control bits control bits control bits brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 00000000 nominal value = 128 10000000 11111111 register set a (a5h) and b (d5h) d7 d6 d5 d4 d3 d2 d1 d0 luminance contrast setting control bits control bits control bits control bits control bits control bits control bits control bits cont7 cont6 cont5 cont4 cont3 cont2 cont1 cont0 gain = 0 00000000 gain = 1/64 00000001 nominal gain = 64 01000000 gain = 127/64 01111111 register set a (a6h) and b (d6h) d7 d6 d5 d4 d3 d2 d1 d0 chrominance saturation setting control bits control bits control bits control bits control bits control bits control bits control bits satn7 satn6 satn5 satn4 satn3 satn2 satn1 satn0 gain = 0 00000000 gain = 1/64 00000001 nominal gain = 64 01000000 gain = 127/64 01111111
preliminary nda required con?dential - nda required page 191 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.5.11 s ubaddress a8 to ae: h orizontal p hase s caling table 162 horizontal luminance scaling increment (sa a8, sa a9; sa d8, sa d9) table 163 horizontal luminance phase offset (sa aa; sa da) table 164 horizontal chrominance scaling increment (sa ac, sa ad; sa dc, sa dd) register set a (a8h ....a9h) and b (d8h ... d9h) a9h / d9h d7..d4 a9h / d9h d3 ..d0 a8h / d8h d7..d4 a8h / d8h d3 ..d0 horizontal luminance scaling increment xscy15..12 xscy11..8 xscy7..4 xscy3..0 scale = 1024/1 (theoretical) zoom 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 scale = 1024/294, lower limit de?ned by data path structure 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 scale = 1024/1023 zoom 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 scale = 1, equals 1024 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 scale = 1024/1025 down scale 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 scale = 1024/8191 down scale 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 register set a (aah) and b (dah) d7 d6 d5 d4 d3 d2 d1 d0 horizontal luminance phase offset control bits control bits control bits control bits control bits control bits control bits control bits xphy7 xphy6 xphy5 xphy4 xphy3 xphy2 xphy1 xphy0 offset = 0 00000000 offset = 1/32 pixel 00000001 offset = 32/32 = 1 pixel 00100000 offset = 255/32 pixel 11111111 register set a (ach ....adh) and b (dch ... ddh) adh / ddh d7..d4 adh / ddh d3 ..d0 ach / dch d7..d4 ach / dch d3 ..d0 horizontal chrominance scaling increment xscc15..12 xscc11..8 xscc7..4 xscc3..0 note: this value must be set to the luminance value xscy / 2 00 00 00 0 0 0 000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
preliminary nda required con?dential - nda required page 192 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 165 horizontal chrominance phase offset (sa ae; sa de) 16.5.12 s ubaddress b0 to bf: v ertical s caling c ontrol table 166 vertical luminance scaling increment (sa b0, sa b1; sa e0, sa e1) table 167 vertical chrominance scaling increment (sa b2, sa b3; sa e2, sa e3) register set a (aeh) and b (deh) d7 d6 d5 d4 d3 d2 d1 d0 horizontal chrominance phase offset control bits control bits control bits control bits control bits control bits control bits control bits xphc7 xphc6 xphc5 xphc4 xphc3 xphc2 xphc1 xphc0 note: this values must be set to xphy/2 00000000 00000001 11111111 register set a (b0h ....b1h) and b (e0h ... e1h) b1h / e1h d7..d4 b1h / e1h d3 ..d0 b0h / e0h d7..d4 b0h / e0h d3 ..d0 vertical luminance scaling increment yscy15..12 yscy11..8 yscy7..4 yscy3..0 scale = 1024/1 (theoretical) zoom 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 scale = 1024/1023 zoom 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 scale = 1, equals 1024 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 scale = 1024/1025 down scale 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 scale = 1/63.999 down scale 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 register set a (b2h ....b3h) and b (e2h ... e3h) b3h / e3h d7..d4 b3h / e3h d3 ..d0 b2h / e2h d7..d4 b2h / e2h d3 ..d0 vertical chrominance scaling increment yscc15..12 yscc11..8 yscc7..4 yscc3..0 note: this value must be set to the luminance value yscy 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
preliminary nda required con?dential - nda required page 193 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 168 vertical scaling mode control (sa b4; sa e4) table 169 vertical phase offsets chroma / luma (sa b8, sa bc; sa e8, sa ec) register set a (b4h) and b (e4h) d4 d0 vertical scaling mode control control bits control bits ymir ymode vertical scaling performs linear interpolation between lines x0 vertical scaling performs higher order accumulating interpolation, better alias suppression x1 no mirroring 0 x lines are mirrored 1 x register set a (b8h) and b (e8h) register set a (bch) and b (ech) d7 d6 d5 d4 d3 d2 d1 d0 vertical phase offsets chroma / luma control bits control bits control bits control bits control bits control bits control bits control bits ypc07 ypy07 ypc06 ypy06 ypc05 ypy05 ypc04 ypy04 ypc03 ypy03 ypc02 ypy02 ypc01 ypy01 ypc00 ypy00 offset = 0 00000000 offset of 32/32 = 1 line 00100000 offset of 255/32 lines 11111111
preliminary nda required con?dential - nda required page 194 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 16.6 programming register - second pll (pll2) and pulse generator 16.6.1 s ubaddress f0 to f5 and ff: second pll (pll2) p rogramming p arameters table 170 number of lfco cycles (= number of clock cycles divided by 4) per line (sa f0, sa f1) table 171 selecting the source of horizontal reference signal for the second pll (pll2) (sa f1) second pll register set (f0h, f1h) f1 h, d0 f0 h, d7...0 splpl8 splpl7 .. splpl0 number of lfco cycles per line (= number of target clock cycles per line divided by 4) target clock frequency = 29,5 mhz (625 lines per frame) 1d8 h target clock frequency = 24,5454 mhz (525 lines per frame) 186 h target clock frequency = 27 mhz (625 lines per frame) 1b0 h target clock frequency = 27 mhz (525 lines per frame) 1ad h calculation formula: splpl[8:0] = (number of target clock cycles per line) / 4 second pll register set (f1 h) d1 second pll (pll2) horizontal reference signal source sphsel the comb?lter decoder is selected as horiz. sync. source. 0 the xrh signal of the x-port (input mode) is selected as horiz. sync. source. 1
preliminary nda required con?dential - nda required page 195 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 172 selecting the operation mode of the second pll (pll2) (sa f1) table 173 loop?lter mode of the second pll (pll2) (sa f1) second pll register set (f1 h) d3 d2 second pll (pll2) operation mode spmod1 spmod1 synthesize clock: the generated (cgc2) frequency depends on the nominal increment (spninc) only. the contribution of the loop ?lter is disabled. the i and p proportion of the loop ?lter is set to zero. 0 0 pll-closed (normal operation mode): this is the normal operation mode of the second pll (pll2): the nominal increment plus the content of loop ?lter de?ne the output (cgc2) frequency. 0 1 pll-hold: the pll keeps the last frequency before entering this mode. the content of the loop ?lter will be frozen. 1 0 pll-re-sync (pll_mode = 11) the phase detector is constantly re-synchronized to the horizontal reference signal. the remaining phase error is fed into the loop ?lter. 1 1 second pll register set (f1 h) d7 .. d4 second pll (pll2) loop filter mode (p- / i-parameter selection) sppi3 .. sppi 0 default adaptive mode (recommended) 0000 fast mode 0001 reserved 0002 . . . 1101 medium mode 1110 slow mode 1111
preliminary nda required con?dential - nda required page 196 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 174 nominal dto increment (sa f2, sa f3) table 175 lock status of the second pll (pll2) (sa f4) second pll register set (f2 h, f3 h) crystal clock frequency f3 h, d7 .. d0 f2 h, d7.. 0 spninc15 .. spninc8 spninc7 .. spninc0 nominal increment for the dto of the second pll (pll2) target clock frequency = 29,5 mhz 32.11 mhz 3acc h 24.576 mhz 4cd2 h target clock frequency = 24,545 mhz 32.11 mhz 30ec h 24.576 mhz 3feb h target clock frequency = 27 mhz 32.11 mhz 35d0 h 24.576 mhz 4650 h calculation formula for the nominal increment depending on the target clock frequency xtalfreq integer of ( (target clock frequency) / ( 4 * xtalfreq ) * 2^16) ) second pll register set (f4 h) d0 lock status of the second pll (pll2) splock second pll (pll2) un-locked 0 second pll (pll2) locked 1
preliminary nda required con?dential - nda required page 197 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 176 maximum phase error threshold for lock detection of the second pll (pll2) (sa ff) second pll register set (ff h) d3 .. d0 maximum phase error threshold for lock detection of the second pll (pll2) spthrm3 .. spthrm0 maximum phase error >= 0 % 0000 maximum phase error >= 6.25 % 0001 maximum phase error >= 12.5 % 0010 maximum phase error >= 18.75 % 0011 maximum phase error >= 25 % 0100 maximum phase error >= 31.5 % 0101 maximum phase error >= 37.5 % 0110 maximum phase error >= 44 % 0111 maximum phase error >= 50 % 1000 maximum phase error >= 56 % 1001 maximum phase error >= 63 % 1010 maximum phase error >= 69 % 1011 maximum phase error >= 75 % 1100 maximum phase error >= 81 % 1101 maximum phase error >= 88 % 1110 maximum phase error >= 94 % 1111
preliminary nda required con?dential - nda required page 198 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 177 number of lines threshold for lock detection of the second pll (pll2) (sa ff) 16.6.2 s ubaddress f6 to fb: p ulse g enerator p rogramming table 178 number of lfco cycles (= number of clock cycles divided by 4) per line (sa f5, sa f6) second pll register set (ff h) d7 .. d4 minimum number of lines while spthrm[3:0] must be smaller than speci?ed before for lock detection of the second pll (pll2) will be indicated spthrl3 .. spthrl0 7 lines 0000 15 lines 0001 23 lines 0010 31 lines 0011 39 lines 0100 47 lines 0101 55 lines 0110 63 lines 0111 71 lines 1000 79 lines 1001 87 lines 1010 95 lines 1011 103 lines 1100 111 lines 1101 119 lines 1110 127 lines 1111 pulse generator register set (f5h, f6h) f6 h, d0 f5 h, d7...0 pglen8 pglen7 .. pglen0 this setting must be equal to the number of lfco cycles per line since it de?nes the output line length at the i-port when driven by the pulse generator target clock frequency = 29,5 mhz (625 lines per frame) 1d8 h target clock frequency = 24,5454 mhz (525 lines per frame) 186 h target clock frequency = 27 mhz (625 lines per frame) 1b0 h target clock frequency = 27 mhz (525 lines per frame) 1ad h calculation formula: pglen[8:0] = (number of target clock cycles per line) / 4
preliminary nda required con?dential - nda required page 199 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 179 selecting the source of horizontal reference signal for the pulse generator (sa f6) table 180 resetting (resynchronizing) the pulse generator to a horizontal synchronisation event. (sa f6) table 181 pulse c trigger position for task a (sa f6, sa f7) pulse generator register set (f6 h) d1 pulse generator horizontal reference signal source for re-synchronisation pghsel the comb?lter decoder is selected as horiz. sync. source. 0 the xrh signal of the x-port (input mode) is selected as horiz. sync. source. 1 pulse generator register set (f6 h) d2 pulse generator horizontal reference signal source for re-synchronisation pgres the pulse generator is in free running mode. 0 software reset/resync for the pulse generator. the internal counter and thus all generated signals (pulse a trigger, pulse b trigger and pulse c trigger) will be resyncronized to the incoming horiz. sync. source (de?ned by pghsel) as long as pulse_gen_res is programmed to 1 1 pulse generator register set for start of line for scaler register set a (f6h ... f7h) f6h d7 ..d4 f7h d7..d4 f7h d3 ..d0 pulse c trigger position for task a data relative to the pulse generator counter measured in clock cycles. pghaps 11...8 pghaps 7...4 pghaps 3...0 lowest value of pulse a 00 0 0 0 0 0 0 0 0 0 0 ... ... ... ... recommended value for itu style receiver operating with sav codes aligned 60e hex (1550 decimal) recommended value for itu style receiver operating with eav codes aligned 60e hex (1550 decimal) ... ... ... ... latest position of pulse a note: if pghaps is greater than pglen * 4 then the pulse a will not be generated! 11 1 1 11 1 1 11 1 1
preliminary nda required con?dential - nda required page 200 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 182 pulse b trigger position for task b (sa f8, sa f9) table 183 pulse c trigger position for sliced vbi data (sa fa, sa fb) pulse generator register set for start of line for scaler register set b (f8h ... f9h) f8h d7 ..d04 f9h d7..d4 f9h d3 ..d0 pulse b trigger position for task b data relative to the pule generator counter measured in clock cycles. pghbps 11...8 pghbps 7...4 pghbps 3...0 lowest value of pulse b 00 0 0 0 0 0 0 0 0 0 0 ... ... ... ... recommended value for itu style receiver operating with sav codes aligned pghbps = pghaps 60e hex (1550 decimal) recommended value for itu style receiver operating with eav codes aligned pghbps = pghaps 60e hex (1550 decimal) ... ... ... ... latest position of pulse b note: if pghbps is greater than pglen * 4 then the pulse b will not be generated! 11 1 1 11 1 1 11 1 1 pulse generator register set for end of line de?nition (fah ... fbh) fah d7 ..d04 fbh d7..d4 fbh d3 ..d0 pulse c trigger position for sliced vbi data relative to the pule generator counter measured in clock cycles. pghcps 11...8 pghcps 7...4 pghcps 3...0 lowest value of pulse c 00 0 0 0 0 0 0 0 0 0 0 ... ... ... ... recommended value for itu style receiver operating with sav codes aligned pghcps = pghbps = pghaps 60e hex (1550 decimal) recommended value for itu style receiver operating with eav codes aligned pghcps = ( pghaps - 48 + ( xd * 2)) mod ( pglen * 4) ... ... ... ... latest position of pulse c note: if pghcps is greater than pglen * 4 then the pulse c will not be generated! 11 1 1 11 1 1 11 1 1
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 201 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required 17 programming start set-up 17.1 decoder part the given values force the following behaviour of the SAA7115 video decoder part: analog input conditions: ntsc m, pal b, d, g, h, i or secam signal in cvbs format on input ai11(column 1) or y/c-format on inputs ai11, ai21 (column 2) analog anti-alias filter and agc active automatic field detection enabled automatic tv/vcr detection enabled automatic color standard detection enabled (column 1 and 2: auto mode 3: predefined filters, sharpness control disabled) standard itu 656 output format enabled on expansion (x) port, see also subaddress 83h (x-port control) contrast, brightness and saturation control in accordance with itu standards adaptive comb filter for luminance and chrominance activated pins llc, llc2, xtout, rts0, rts1 and rtco are set to 3-state i-port (scaled video-output) and audio clock generation are disabled (lower power consumption), see corresponding sections to a ctivate their functionality. columns 3 to 5 are examples for typical settings in non auto mode. table 184 decoder part start set-up values for auto mode and the three main standards sub addr. (hex) register function control names (1) remarks values (hex) (1) full auto mode (cvbs) (2) full auto mode (y/c) (3) ntsc m (cvbs) (4) pa l b , d, g, h and i (cvbs) (5) secam (cvbs) 00 chip version id7 to id0 read only 01 increment delay aosl2, wpoff, gudl1, gudl0 and idel3 to idel0 white peak control activated 08 08 08 08 08 02 analog input control 1 fuse1, fuse0, x,x, and mode3 to mode0 cvbs signal expected at input ai11 (cvbs-modes) y signal expected at input ai11, c signal expected at input ai21 (y/c-mode) c0 c8 c0 c0 c0
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 202 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required 03 analog input control 2 x, hlnrs, vbsl, cpoff, holdg, gafix, gai28 and gai18 agc active with long vertical blanking, color peak control active 20 20 20 20 20 04 analog input control 3 gai17 to gai10 no in?uence 90 90 90 90 90 05 analog input control 4 gai27 to gai20 no in?uence 90 90 90 90 90 06 horizontal sync start hsb7 to hsb0 just an example eb eb eb eb eb 07 horizontal sync stop hss7 to hss0 just an example e0 e0 e0 e0 e0 08 sync control aufd, fsel, foet, htc1, htc0, hpll, vnoi1 and vnoi0 automatic ?eld detection active, automatic time constant setting active, vertical noise reduction active b0 b0 b0 b0 b0 09 luminance control byps, ycomb, ldel, lubw and lufi3 to lufi0 lubw and lufi controls are automatically adjusted via auto[1:0] = 01 (= auto mode 3), therefore these settings take only effect at lower auto levels! 40 80 40 40 1b 0a luminance brightness control dbri7 to dbri0 default brightness 80 80 80 80 80 0b luminance contrast control dcon7 to dcon0 default contrast 44 44 44 44 44 0c chrominance saturation control dsat7 to dsat0 default saturation 40 40 40 40 40 0d chrominance hue control huec7 to huec0 default hue 00 00 00 00 00 sub addr. (hex) register function control names (1) remarks values (hex) (1) full auto mode (cvbs) (2) full auto mode (y/c) (3) ntsc m (cvbs) (4) pa l b , d, g, h and i (cvbs) (5) secam (cvbs)
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 203 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required 0e chrominance control 1 cdto, cstd2 to cstd0, dcvf, fctc, auto0 and ccomb dcvf control is automatically adjusted via auto[1:0] = 01or 10 (= auto modes 2 and 3), therefore this setting takes only effect in auto modes 0 or 1 (auto[1:0] = 00 or 11) 07 07 8d 85 d4 0f chrominance gain control acgc and cgain6 to cgain0 automatic color gain control active via acgc = 0, cgain setting has no effect 2a 2a 2a 2a 2a 10 chrominance control 2 offu1, offu0, offv1, offv0, chbw and lcbw2 to lcbw0 auto level 3 active in column 1 and 2, chbw and lcbw settings have no effect 06 06 06 06 00 11 mode/delay control colo, rtp1, hdel1, hdel0, rtp0 and ydel2 to ydel0 automatic color killer active 00 00 00 00 00 12 rt signal control rtse13 to rtse10 and rtse03 to rtse00 rts0 and rts1 are tristated 00 00 00 00 00 13 rt/x-port output control rtce, xrhs, xrvs1, xrvs0, hlsel and ofts2 to ofts0 rtco is tristated, xport output format is set to itu656-mode 00 00 00 00 00 14 analog/adc/compatibility control cm99, uptcv, aosl1, aosl0, xtoute, auto1, apck1 and apck0 analog output is disabled, crystal clock output is disabled, default adc sample phase selected 01 01 01 01 01 15 vgate start, fid change vsta7 to vsta0 just an example 11 11 11 11 11 16 vgate stop vsto7 to vsto0 just an example fe fe fe fe fe 17 miscellaneous, vgate con?guration and msbs llce, llc2e, laty2 to laty0, vgps, vsto8 and vsta8 llc and llc2-outputs tristated, standard search latency is set to 3 ?elds (default) d8 d8 d8 d8 d8 sub addr. (hex) register function control names (1) remarks values (hex) (1) full auto mode (cvbs) (2) full auto mode (y/c) (3) ntsc m (cvbs) (4) pa l b , d, g, h and i (cvbs) (5) secam (cvbs)
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 204 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required 18 raw data gain control rawg7 to rawg0 default raw data gain 40 40 40 40 40 19 raw data offset control rawo7 to rawo0 default raw data offset 80 80 80 80 80 1a quam/secam color killer levels qthr3 to qthr0, sthr3 to sthr0 default color killer thresholds 77 77 77 77 77 1b tv/vcr-detection sensitivity, xport output format (msb), automatic color limiter, fast sequence correction control atvt1 to atvt0, x, ofts3, x, acol, fsqc default tv/vcr-switch sensitivity, xport output format 8 bit, automatic color limiter active, noise insensitive pal/secam sequence correction 42 42 42 42 42 1c enhanced comb?lter control 1 hodg1 to hodg0, vedg1 to vedg0, medg1 to medg0, cmbt1 to cmbt0, vedt1 to vedt0 default comb?lter parameters a9 a9 a9 a9 a9 1d enhanced comb?lter control 2 x, x, x, x, x, x, vedt1 to vedt0 default comb?lter parameters 01 01 01 01 01 1e status byte 1 video decoder nfld, hlck, sltca, glimt, glimb, wipa, dcstd1 and dcstd0 read only 1f status byte 2 video decoder intl, hlvln, fidt, sttb, type3, colstr, copro and rdcap read only sub addr. (hex) register function control names (1) remarks values (hex) (1) full auto mode (cvbs) (2) full auto mode (y/c) (3) ntsc m (cvbs) (4) pa l b , d, g, h and i (cvbs) (5) secam (cvbs)
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 205 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required note 1. all x values must be set to logic 0. 41 to 57 line control registers (located in the data slicer section) lcr02[7:0] to lcr24[7:0] request processed video data type for all lines at xport 00 00 00 00 00 83 xport io control registers (located in the scaler global section) xpck1 to xpck0, xrqt, xpe1 to xpe0 enable xport output with correct timing 31 31 31 31 31 88 power save control registers (located in the scaler global section) xpck1 to xpck0, xrqt, xpe1 to xpe0 enable only the required adcs and the video decoder, switch scaler and audio clock generation into sleep mode. 4a ca 4a 4a 4a sub addr. (hex) register function control names (1) remarks values (hex) (1) full auto mode (cvbs) (2) full auto mode (y/c) (3) ntsc m (cvbs) (4) pa l b , d, g, h and i (cvbs) (5) secam (cvbs)
preliminary nda required con?dential - nda required page 206 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 17.2 audio clock generation part the given values force the following behaviour of the SAA7115 audio clock generation part: used crystal is 24.576 mhz expected field frequency is 59.94 hz (e.g. ntsc m standard) generated audio master clock frequency at pin amclk is 256 44.1 khz = 11.2896 mhz amclk is frame-locked to the incoming video signal amclk is directly generated by the audio clock pll, no cgc2 is used amclk is externally connected to amxclk [short-cut between pins 37 and 41] asclk (bit clock) = 32 44.1 khz = 1.4112 mhz alrclk (word select) is 44.1 khz. table 185 audio clock part set-up values note 1. all x values must be set to logic 0. 2. see also chapter 8.7: audio clock generation (subaddresses 30h to 3fh) for more examples. sub address (hex) register function bit name (1) start values 76543210hex 30 audio master clock cycles per ?eld; bits 7 to 0 acpf7 to acpf0 1 0111100 bc 31 audio master clock cycles per ?eld; bits 15 to 8 acpf15 to acpf8 1 1011111 df 32 audio master clock cycles per ?eld; bits 17 and 16 x, x, x, x, x, x, acpf17 and acpf16 0 0000010 02 33 reserved x, x, x, x, x, x, x, x 0 0000000 00 34 audio master clock nominal increment; bits 7 to 0 acni7 to acni0 1 1001101 cd 35 audio master clock nominal increment; bits 15 to 8 acni15 to acni8 1 1001100 cc 36 audio master clock nominal increment; bits 21 to 16 x, x, acni21 to acni16 0 0111010 3a 37 reserved x, x, x, x, x, x, x, x 0 0000000 00 38 clock ratio amxclk to asclk x, x, sdiv5 to sdiv0 0 0000011 03 39 clock ratio asclk to alrclk x, x, lrdiv5 to lrdiv0 0 0010000 10 3a audio clock generator basic set-up ucgc, cgcdiv, x, x, apll, amvr, lrph, scph 00000000 00 3b to 3f reserved x, x, x, x, x, x, x, x 0 0000000 00
preliminary nda required con?dential - nda required page 207 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 17.3 data slicer and data type control part the given values force the following behaviour of the SAA7115 vbi-data slicer part: closed captioning data are expected at line 21 of field 1 (60 hz/525 line system) all other lines are processed as active video sliced data are framed by itu 656 like sav/eav sequence, no re-coding of data bytes. sliced data packages for all defined vbi standards, see table 107: sliced data output modes (sa 5d) example for itu656 correct line counting, field id of vbi slicer is swapped (see 8.2 and 8.4) table 186 data slicer start set-up values notes 1. all x values must be set to logic 0. 2. changes for 50 hz/625 line systems: subaddress 5ah = 03h and subaddress 5bh = 03h. sub address (hex) register function bit name (1) start values 76543210hex 40 slicer control 1 chkwss, ham_n, fce, hunt_n, x, x, x, x 01000000 40 41 to 53 line control register 2 to 20 lcrn_7 to lcrn_0 (n = 2 to 20) 00000000 00 54 line control register 21 lcr21_7 to lcr21_0 01000000 4f 55 to 57 line control register 22 to 24 lcrn_7 to lcrn_0 (n = 22 to 24) 00000000 00 58 programmable framing code fc7 to fc0 00000000 00 59 horizontal offset for slicer hoff7 to hoff0 01000111 47 5a vertical offset for slicer voff7 to voff0 0000011006 (2) 5b ?eld offset and msbs for horizontal and vertical offset foff, x, vep, voff8, x, hoff10 to hoff8 1000001183 (2) 5c reserved x, x, x, x, x, x, x, x 00000000 00 5d sliced data output mode x, x, x, sldom4 to sldom0 00001100 0c 5e sliced data identi?cation code x, x, sdid5 to sdid0 00000000 00 5f reserved x, x, x, x, x, x, x, x 00000000 00 60 slicer status byte 0 - , fc8v, fc7v, vpsv, ppv, ccv, - , - read-only register 61 slicer status byte 1 - , - , f21_n, ln8 to ln4 read-only register 62 slicer status byte 2 ln3 to ln0, dt3 to dt0 read-only register
preliminary nda required con?dential - nda required page 208 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 17.4 scaler and interfaces table 187 shows some examples for the scaler programming with: prsc = prescale ratio fisc = fine scale ratio vsc = vertical scale ratio. the ratio is defined as: in the following settings the vbi-data slicer is inactive. to activate the vbi-data slicer, sldom 5dh[4:0] has to be set to > 00h. to compensate the running-in of the vertical scaler, the vertical input window lengths are extended by 2 to 290 lines, respectively 242 lines for xs, but the scaler increment calculations are done with 288, respectively 240 lines. trigger condition for trigger condition strc[1:0]90h[1:0] not equal 00. if the value of (yo + ys) is greater equal 262 (ntsc), respectively 312 (pal) the output field rate is reduced to 30 hz, respectively 25 hz. horizontal and vertical offsets (xo and yo) have to be used to adjust the displayed video in the display window. as this adjustment is application dependent, the listed values are only dummy values. maximum zoom factor the maximum zoom factor is dependent on the back-end data rate and therefore back-end clock and data format dependent (8 or 16-bit output). the maximum horizontal zoom is limited to about 3.5, due to internal data path restrictions. number of input pixel number of output pixel ---------------------------------------------------------- -
preliminary nda required con?dential - nda required page 209 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 17.4.1 e xamples table 187 example con?gurations example number scaler source and reference events input window output window scale ratios 1 analog input to 8-bit i-port output, with sav/eav codes and 8010 blanking, 8-bit serial byte stream decoder output at x-port; acquisition trigger at rising edge vertical and rising edge horizontal reference signal; 1 active h and v-gates on igph and igpv, igp0 = ?eld id, igp1 = sliced vbi data ?ag, impak = 1 = the pulse generator need to be programmed (addr. 0xf5 to 0xfb) idq quali?er logic 1 active 720 240 720 240 prsc = 1; ?sc = 1; vsc = 1 2 window de?nitions and scale ratio according sqp ntsc-m analog input to 8-bit i-port output, with sav/eav codes and 8010 blanking, 8-bit serial byte stream decoder output at x-port; acquisition trigger at rising edge vertical and rising edge horizontal reference signal; 1 active h and v-gates on igph and igpv, igp0 = ?eld id, igp1 = sliced vbi data ?ag, impak = 1 = the pulse generator need to be programmed (addr. 0xf5 to 0xfb) pll2 clock used (icks[1:0] = 2), refer to section 17.5 , example 2 idq quali?er logic 1 active 704 240 640 240 prsc = 1; ?sc = 1.1; vsc = 1 3 window de?nitions and scale ratio according sqp pal-bg analog input to 16-bit output, without sav/eav codes, y on i-port, c b -c r on h-port and decoder output at x-port; acquisition trigger at rising edge vertical and rising edge horizontal reference signal; 1 active h-gate and v-sync on igph and igpv, igp0= ?eld id, igp1 = ?lled ?ag, impak = 1 = the pulse generator need to be programmed (addr. 0xf5 to 0xfb) pll2 clock used (icks[1:0] = 2) refer to sect.17.5 , example 3 idq = cref like quali?er at (pll2 clock )/2 data rate 704 288 768 288 prsc = 1; ?sc = 0.91667; vsc = 1 4 x-port input 8 bit with sav/eav codes, no reference signals on xrh and xrv, xclk as gated clock; ?eld detection and acquisition trigger on different events; acquisition triggers at falling edge vertical and rising edge horizontal; i-port output 8 bit with sav/eav codes like example number 1 720 240 352 288 prsc = 2; ?sc = 1.022; vsc = 0.8333 5 x-port and h-port for 16-bit y-cb-c r4:2:2 input (if no 16-bit output selected); xrh and xrv as references; ?eld detection and acquisition trigger at falling edge vertical and rising edge horizontal; i-port output 8 bit with sav/eav codes, but y only output 720 288 200 80 prsc = 2; ?sc = 1.8; vsc = 3.6
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 210 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required table 188 scaler and interface con?guration example i 2 c-bus address (hex) main functionality example 1 example 2 example 3 example 4 example 5 hex dec hex dec hex dec hex dec hex dec global settings 80 task enable, idq and back-end clock de?nition 90 - 92 - 9a - 10 - 10 - 81 v-blanking and fid source selection 00 - 00 - 00 - 00 - 00 - 83 xclk output phase and x-port output enable 31 - 31 - 31 - 10 - 10 - 84 igph, igpv, igp0 and igp1 output de?nition 80 - 80 - 04 - a0 - a0 - 85 signal polarity control and i-port byte swapping 00 - 00 - 00 - 10 - 10 - 86 fifo ?ag thresholds, video enable and data packing, if impak = 1, the pulse generator needs to be programmed (addr. 0xf5 to 0xfb) c5 - c5 - ea - 45 - 45 - 87 iclk and idq output phase and i-port enable 31 - 31 - 31 - 31 - 31 - 88 power save control and software reset f0 - f0 - f0 - f0 - f0 - task a: scaler input con?guration and output format settings 90 task handling 00 - 00 - 00 - 00 - 00 - 91 scaler input source and format de?nition 08 - 08 - 08 - 18 - 38 - 92 reference signal de?nition at scaler input 00 - 00 - 00 - 19 - 11 - 93 i-port output formats and con?guration c0 - c0 - 00 - c0 - 84 - input and output window de?nition 94 horizontal input offset (xo) 04 4 10 16 10 16 04 4 04 4 95 00 - 00 - 00 - 00 - 00 - 96 horizontal input (source) window length (xs) d0 720 c0 704 c0 704 d0 720 d0 720 97 02 - 02 - 02 - 02 - 02 - 98 vertical input offset (yo) 07 263 07 263 39 313 0a 10 0a 10 99 01 - 01 - 01 - 00 - 00 - 9a vertical input (source) window length (ys) 06 262 06 262 38 312 f2 242 22 290 9b 01 - 01 - 01 - 00 - 01 - fmod bit d7 11111 1 0 0 0 0
philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 con?dential - nda required page 211 filename: SAA7115_datasheet.fm last edited by h. lambers preliminary nda required 9c horizontal output (destination) window length (xd) d0 720 80 640 00 768 60 352 c8 200 9d 02 - 02 - 03 - 01 - 00 - 9e vertical output (destination) window length (yd) 07 263 07 263 39 313 20 288 50 80 9f 01 - 01 - 01 - 01 - 00 - pre?ltering and prescaling a0 integer prescale (value 00 not allowed) 01 - 01 - 01 - 02 - 02 - a1 accumulation length for prescaler 00 - 00 - 00 - 02 - 03 - a2 fir pre?lter and prescaler dc normalization 00 - 00 - 00 - aa - f2 - a4 scaler brightness control 80 128 80 128 80 128 80 128 80 128 a5 scaler contrast control 40 64 40 64 40 64 40 64 11 17 a6 scaler saturation control 40 64 40 64 40 64 40 64 11 17 horizontal phase scaling a8 horizontal scaling increment for luminance 00 1024 66 1126 aa 938 18 1048 34 1844 a9 04 - 04 - 03 - 04 - 07 - aa horizontal phase offset luminance 00 - 00 - 00 - 00 - 00 - ac horizontal scaling increment for chrominance 00 512 33 563 d5 469 0c 524 9a 922 ad 02 - 02 - 01 - 02 - 03 - ae horizontal phase offset chrominance 00 - 00 - 00 - 00 - 00 - vertical scaling b0 vertical scaling increment for luminance 00 1024 00 1024 00 1024 55 853 66 3686 b1 04 - 04 - 04 - 03 - 0e - b2 vertical scaling increment for chrominance 00 1024 00 1024 00 1024 55 853 66 3686 b3 04 - 04 - 04 - 03 - 0e - b4 vertical scaling mode control 00 - 00 - 00 - 00 - 01 - b8 to bf vertical phase offsets luminance and chrominance (need to be used for interlace correct scaled output) start with b8 to bf at 00h, if there are no problems with the interlaced scaled output optimize according to section 8.3.3.2 start with b8 to bf at 00h, if there are no problems with the interlaced scaled output optimize according to section 8.3.3.2 i 2 c-bus address (hex) main functionality example 1 example 2 example 3 example 4 example 5 hex dec hex dec hex dec hex dec hex dec
preliminary nda required con?dential - nda required page 212 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 17.5 pll2 and pulse generator control part the given values force the following behaviour of the SAA7115 pll2 clock and pulse generation part, where the pulse generation values are for 8 bit i-port output with itu like code sequences: example 1: pll2 - synthesis of line locked square pixel clock of 24.545454 mhz from 24.576 mhz crystal pulse generator - pulse generation for 1560 clock cycles per line and video (640 pixel=1288 bytes) from page a and raw data (1448 bytes) from page b, no deep buffering, delay only used for eav alignment, vbi stream as timing master a corresponding scaler programming (only for page a) can be found in sect. 17.4 , example 2 example 2: pll2 - synthesis of line locked square pixel clock of 29.5 mhz from 32.11 mhz crystal pulse generator - pulse generation for 1888 clock cycles per line and video a (768 pixel=1544 bytes) + sliced vbi, eav aligned, medium pixel buffering, pghcps somewhere in the allowed range a corresponding scaler programming can be found in sect. 17.4 , example 3 pll2 in normal operation (spmod[1:0] = 01) for all examples for 32.11 mhz crystal (external strapping resistor required)
preliminary nda required con?dential - nda required page 213 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 table 189 pll2 and pulse generator start set-up values notes 1. all x values must be set to logic 0. 2. max. values for pulse positions are 4 x pglen[8:0], e.g. pglen = 429, pghxps max = 1716. 3. the position counter starts with count 1, for the value of 0 no trigger pulses are generated sub address (hex) register function bit name (1) example 1 example 2 hex dec hex dec f0 lfcos per line (lsbs) splpl7 to splpl0 86 390 d8 472 f1 pi-parameter selection, pll mode, pll-hsync-selection, lfcos per line (msb) sppi3 to sppi0, spmod1, spmod0, sphsel, splpl8 05 05 f2 nominal pll2 dto increment (lsbs) spninc7 to spninc0 eb 16363 cc 15052 f3 nominal pll2 dto increment (msbs) spninc15 to spninc8 3f 3a f4 pll2 lock status - , - , -, -, -, -, -, splock f5 pulse generator line length (lsbs) pglen7 to pglen0 86 390 d8 472 f6 pulse a position (lsbs), pulsegen resync and hsync selection, pulse generator line length (msb) pghaps3 to pghaps0, x, pgres, pghsel, pglen8 01 c1 f7 pulse a position (msbs) pghaps11 to pghaps4 13 304 2b 700 f8 pulse b position (lsbs) pghbps3 to pghbps0,x,x,x,x 00 144 00 0 f9 pulse b position (msbs) pghbps11 to pghbps4 09 00 fa pulse c position (lsbs) pghcps3 to pghcps0,x,x,x,x 00 1536 c0 300 fb pulse c position (msbs) pghcps11 to pghcps4 60 12 fc to fe reserved x, x, x, x, x, x, x, x 00 0 00 0 ff pll locking thresholds spthrl3 to spthr0, spthrm3 to spthrm0 88 136 88 136
preliminary nda required con?dential - nda required page 214 filename: SAA7115_datasheet.fm last edited by h. lambers philips semiconductors cvip2 date: 10/23/01 cs-pd hamburg datasheet SAA7115 version: 0.67 18 package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 1.6 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.25 15.75 1.15 0.85 7 0 o o 0.08 0.08 0.2 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot407-1 136e20 ms-026 00-01-19 00-02-01 d (1) (1) (1) 14.1 13.9 h d 16.25 15.75 e z 1.15 0.85 d b p e q e a 1 a l p detail x l (a ) 3 b 25 c d h b p e h a 2 v m b d z d a z e e v m a x 1 100 76 75 51 50 26 y pin 1 index w m w m 0 5 10 mm scale lqfp100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm sot407-1

▲Up To Search▲

Price & Availability of SAA7115

	To Download SAA7115 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .